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The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task. The frequency modulation dynamics are analyzed for this architecture. The results are employed to implement a SiGe BiCMOS fully integrated 75–83 GHz frequency-modulated continuous-wave synthesizer. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism together with the dual-loop PLL architecture provides low loop bandwidth variation over the whole output frequency range, −97 dBc/Hz phase noise at 1-MHz offset, and maximal modulation rate of 100 GHz/ms. [ABSTRACT FROM AUTHOR]

Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13-\mu\m SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB) de-modulator, tunable BB filter, phase-locked loop (PLL) synthesizer, and a frequency quadrupler. At room temperature the Rx chips achieve a maximum gain of 73 dB, 6-dB noise figure, better than -\12-dBm input third-order intercept point, more than 65-dB dynamic range, and consume 600 mW for lower band (LB) (71–76 GHz) and higher band (HB) (81–86 GHz) alike. The transmitter (Tx) chips include a power amplifier, image reject driver, variable RF attenuators, power detector, IF-to-RF up-converting mixer, IF VGA, quadrature BB-to-IF modulator, PLL, and a frequency multiplier. The Tx chips achieve a power 1-dB compression point (P1dB) of 17.5/16.6 dBm, saturated power (Psat) of 20.5/18.8 dBm on a single-ended output, up to 39-dB gain with an analog controlled dynamic range of 30 dB, and consumes 1.75/1.8 W for the LB and HB, respectively. This state-of-the-art performance enables the usage of complex modulations and high-capacity transmission. [ABSTRACT FROM PUBLISHER]

Broadcast traditionally has been regarded as a prohibitive communication transaction in multiprocessor environments. Nowadays, such a constraint largely drives the design of architectures and algorithms all-pervasive in diverse computing domains, directly and indirectly leading to diminishing performance returns as the many-core era is approaching. Novel interconnect technologies could help revert this trend by offering, among others, improved broadcast support, even in large-scale chip multiprocessors. This article outlines the prospects of wireless on-chip communication technologies pointing toward low-latency (a few cycles) and energy-efficient broadcast (a few picojoules per bit). It also discusses the challenges and potential impact of adopting these technologies as key enablers of unconventional hardware architectures and algorithmic approaches, in the pathway of significantly improving the performance, energy efficiency, scalability, and programmability of many-core chips. [ABSTRACT FROM PUBLISHER]

A promising solution to continue the complementary metal-oxide semiconductor (CMOS) scaling roadmap at the 22 nm technology node and beyond is CMOS-silicon on insulator (SOI), which is used especially in low-power and "system on chip" applications [1]. CMOS-SOI involves building conventional MOSFETs on very thin layers of crystalline silicon. The thin layer of silicon is separated from the substrate by a thick layer of buried SiO2 film, thus isolating the devices from the underlying silicon substrate and from each other. CMOS-SOI technology is already a leading technology in a wide range of applications where integrated CMOS-SOI-microelectromechanical systems or nanoelectromechanical systems (MEMS/NEMS) technologies provide unique sensing systems for IR and terahertz (THz) imagers. [ABSTRACT FROM PUBLISHER]

This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical wideband circuit level models have been developed based on explicit expressions. The pronounced frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as skin and proximity effects. The models have been verified against numerical computations (full wave HFSS and quasi-static Q3D solvers). A dedicated test site has been designed for broadband characterization (from 1 MHz up to 110 GHz) of TSVs within a dense farm. [ABSTRACT FROM PUBLISHER]

Presents a study which looked at the implementation of a signal space for microwave nonlinear-network analysis. Propose of a nonlinear microwave network analysis; Relation between the time-domain currents and voltage for a memoryless two-port network; Investigation of the accuracy of the signal-space approach.