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International audience; The immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications. This paper presents a design of such an oscillator with a high frequency resolution and small area in 28 nm technology. In order to reduce the dependence of the oscillator frequency on its voltage supply, differential amplifiers are used as inverters (delay cells) and a bias circuit with a stable voltage output is employed to bias the oscillator. From post-layout simulations, this DCO achieves a dynamic range from 1.13 to 1.54 GHz with the use of differential delay cells, the variation of the output frequency is less than 4.5% over all the frequency range, for VDD variation of 10%. The frequency control has 9.2 bits, giving an average frequency step of 722 kHz. This DCO achieves a phase noise of-74 dBc/Hz@1MHz or an jitter equivalence of 2.3 ps. The maximal power consumption of this DCO at maximum frequency is 840 µW, which is a low figure comparing to the state-of-the-art implementation with typical power of sub-milliwatts for the similar frequency range. Index Terms-All-Digital Phase Locked Loop (ADPLL), Digitally controlled oscillator (DCO), differential inverter ring

In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.

International audience; In this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.