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This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 &mu, m SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of &minus, 39.6 to approximately &minus, 51.8 dB with a &minus, 3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 &times, 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.