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The main purpose of this work has been to carry out a complete analysis by simulation of the behavior of low-voltage power MOSFETs accounting for the effects of the gate parasitic-RC distribution. The use of a gate-mesh low resistance has been analyzed as an overall alternative to more traditional materials. Moreover, a design using mixed materials (poly-silicon material and low resistivity one) has been also investigated. The contribution of the gate metal resistivity has been accounted for through modeling and simulation runs. This study is devoted to the decrease of the switching speed, thus allows obtaining advantageous performances in terms of power losses. Moreover good results are shown that can be achieved in terms of robustness due to a more uniform distribution of the current in switching condition within the device structure. The analysis has been realized by building a complete model of the device useful for behavioral simulations based on a preliminary discretization of the geometry into elementary cells. The achieved results can be exploited to improve the device design especially from the point of view of a continuous scaling process. The increase of the switching speed allows managing both higher powers and operative frequency as it is required by new converters and more demanding applications.

A new power structure integrating a freewheeling diode in the termination region of a punch-through (PT) insulated gate bipolar transistor (IGBT) is presented. The proposed solution requires virtually no silicon area penalty with respect to a standard IGBT. Static and dynamic experimental results show the correct behavior of both IGBT and freewheeling diode. Further, it is shown that the lateral diode surrounding the multicellular IGBT can support IGBT direct current with low on-state voltage drop. The operation mechanisms of the composite structure and design techniques to improve structure dynamic behavior are investigated through two-dimensional numerical device simulations.

The need of devices for medium-range power converters gives rise to a growing interest for the series connections of IGBTs. In this case the control of the voltage sharing across the string of series-connected devices as well as their protection during the short circuit transients are important issues. In this paper is presented an exhaustive analysis of the electrical quantities and device parameters affecting the voltage sharing across the series strings of IGBTs in short circuit conditions In particular, hard switching fault (HSF) and fault under load (FUL) are investigated, in the case of series connections of devices, by carrying out simulation runs and experimental tests in order to understand the behavior of the IGBTs in these critical conditions. Advantages and disadvantages of the voltage sharing techniques are discussed with reference to the failure in short-circuit occurring on the series connection of devices.

The paper deals with the short circuit behavior during fault under load (FUL) conditions occurring on IGBT devices. The experimental switching transients in FUL with inductive load have been widely investigated. The devices have been tested in several working conditions accounting for the spread of the device characteristics, the parasitic due to the board layout, and the gate driving characteristics aiming to evaluate the switching performances and the influence of the parameters involved into the transient. The effect of the device temperature has been taken into account too. The experimental tests have been carried out using as a workbench a chopper circuit equipped with IGBT devices. As in medium and large power range converters the use of multiple string of IGBT devices is worth to be considered, the parallel and series connections experiencing FUL conditions have been also investigated.

In this paper the behavior analysis of parallel connection of IGBTs under short circuit conditions is presented. The issues of hard switching fault (HSF) and fault under load (FUL) short circuit types are faced by taking into account for the influence of the layout and gate driving parameters. The role of the temperature has been considered too in order to investigate how this quantity affects the IGBTs short circuit phenomenon. An analytical description of the FUL transient is introduced to put in correlation the current and voltage peaks, which are suffered by the IGBT, to the circuit and device parameters. Indeed, the current peak imbalance appearing in a FUL condition is depending on the power layout, on the gate driving conditions and spread on device parameters.

Aluminum-based metallizations are extensively used as electrical interconnections of integrated power microelectronic devices. It is well known that this metal exposed to moisture is highly sensitive to corrosion due to the chemical interaction of aluminum with water. In this paper we report a study of some Al passivation treatments against moisture corrosion, The proposed treatment can be done on the finished wafer without any damage of other device materials and satisfies the die attach and wire-bonding requirements. It consists of a simple chemical dipping into an organic bath containing a phosphating agent. The passivation behavior of the resulting surfaces has been checked by means of pressure cooker test both on the wafer and power metal oxide semiconductor devices assembled in plastic packages. The surfaces resulting in each process step have been analyzed by means of electron spectroscopy for chemical analysis, The passivated surface is formed of one to two monolayers of ortho- and polyphosphate phases directly grafted onto the alumina surface, The same growth process allows fluorine surface contamination reduction.

A new PSpice model of power MOSFETs has been developed aiming to account for the parameter variations with the temperature. A new computer aided design package that helps the designer in the parameter extraction procedure is discussed in detail. The model accuracy has been tested by comparison of the simulated waveforms with the experimental traces relative to actual devices.

A new PSpice model of punch-through (PT) IGBTs is developed to account for the presence of the buffer layer and its influence on the dynamic behavior of the device. The recombination and redistribution of charge in the base region of IGBTs during a transient behavior are modeled and represented by equivalent electric circuits. In particular, the effect of the external voltage (clamping voltage) on the tail current decay is modeled. Besides, phenomena such as the "tail bump" and the variation of the slope in the initial part of the output voltage V/sub ce/ during a turn-off transient are modeled. The proposed model is validated by comparing several simulation runs to the experimental traces at different static and dynamic working conditions.

A new PSpice model of power MOSFETs has been developed aiming to account for the parameter variations with the temperature. The paper discusses the new model in detail, showing the close correlation between the new quantities introduced and the experimental evidence that requires an improvement of the simulations carried out by similar available models. Comparison and evaluations of simulation runs (in static and dynamic conditions) obtained by the proposed model and other power MOSFET PSpice models are also presented and discussed. Finally, performances in terms of accuracy, simulation times, advantages and disadvantages of each model in different circuit applications are reported and compared with the experimental traces relative to actual devices.

In this paper a novel SPICE-based simulation tool is presented, suitable to describe the steady-state electro-thermal behavior of new-generation multicellular VDMOS transistors for low-voltage applications. Compared to similar approaches, the proposed one presents substantial improvements: (a) a new electrothermal sub-circuit representation for the elementary transistor is used, which provides an accurate prediction of device characteristics over the temperature range [300 K-400 K] also in quasi-saturation operating mode; (b) the thermal network accounts for both self-heating and thermal interaction effects, is based solely on layout data and is automatically generated; (c) non linear thermal phenomena and layout effects are taken into account.