Search

Although near-term quantum computing devices are still limited by the quantity and quality of qubits in the so-called NISQ era, quantum computational advantage has been experimentally demonstrated. Moreover, hybrid architectures of quantum and classical computing have become the main paradigm for exhibiting NISQ applications, where low-depth quantum circuits are repeatedly applied. In order to further scale up the problem size solvable by the NISQ devices, it is also possible to reduce the number of physical qubits by "cutting"the quantum circuit into different pieces. In this work, we experimentally demonstrated a circuit-cutting method for simulating quantum circuits involving many logical qubits, using only a few physical superconducting qubits. By exploiting the symmetry of linear-cluster states, we can estimate the effectiveness of circuit-cutting for simulating up to 33-qubit linear-cluster states, using at most 4 physical qubits for each subcircuit. Specifically, for the 12-qubit linear-cluster state, we found that the experimental fidelity bound can reach as much as 0.734, which is about 19% higher than a direct implementation on the same 12-qubit superconducting processor. Our results indicate that circuit-cutting represents a feasible approach of simulating quantum circuits using much fewer qubits, while achieving a much higher circuit fidelity.

Quantum error correction is an essential ingredient for universal quantum computing. Despite tremendous experimental efforts in the study of quantum error correction, to date, there has been no demonstration in the realisation of universal quantum error-correcting code, with the subsequent verification of all key features including the identification of an arbitrary physical error, the capability for transversal manipulation of the logical state and state decoding. To address this challenge, we experimentally realise the [5, 1, 3] code, the so-called smallest perfect code that permits corrections of generic single-qubit errors. In the experiment, having optimised the encoding circuit, we employ an array of superconducting qubits to realise the [5, 1, 3] code for several typical logical states including the magic state, an indispensable resource for realising non-Clifford gates. The encoded states are prepared with an average fidelity of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{upgreek} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} }{}$57.1(3)\%$\end{document} while with a high fidelity of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{upgreek} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} }{}$98.6(1)\%$\end{document} in the code space. Then, the arbitrary single-qubit errors introduced manually are identified by measuring the stabilisers. We further implement logical Pauli operations with a fidelity of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{upgreek} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} }{}$97.2(2)\%$\end{document} within the code space. Finally, we realise the decoding circuit and recover the input state with an overall fidelity of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{upgreek} \usepackage{mathrsfs} \setlength{\oddsidemargin}{-69pt} \begin{document} }{}$74.5(6)\%$\end{document}, in total with 92 gates. Our work demonstrates each key aspect of the [5, 1, 3] code and verifies the viability of experimental realisation of quantum error-correcting codes with superconducting qubits., Experimental demonstration of encoding, decoding, logical operation, and error detection of a five-qubit error correcting code on a superconducting quantum processor.

This paper presents several component prototypes towards a low-latency, small-form-factor optical link designed for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade. A prototype of the custom-made dual-channel optical transmitter module, the Miniature optical Transmitter (MTx), with separate transmitter optical sub-assemblies (TOSAs) has been demonstrated at data rates up to 8 Gbps per channel. A Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC has been developed and is used in the current MTx prototypes. A serializer ASIC prototype, operating at up to 8 Gbps per channel, has been designed and tested. A low-latency, low-overhead encoder ASIC prototype has been designed and tested. The latency of the whole link, including the transmitter latency and the receiver latency but not the latency of the fiber, is estimated to be less than 57.9 ns. The size of the MTx is 45 mm x 15 mm x 6 mm., 12 pages, 13 figures

Quantum error correction is a critical technique for transitioning from noisy intermediate-scale quantum (NISQ) devices to fully fledged quantum computers. The surface code, which has a high threshold error rate, is the leading quantum error correction code for two-dimensional grid architecture. So far, the repeated error correction capability of the surface code has not been realized experimentally. Here, we experimentally implement an error-correcting surface code, the distance-3 surface code which consists of 17 qubits, on the \textit{Zuchongzhi} 2.1 superconducting quantum processor. By executing several consecutive error correction cycles, the logical error can be significantly reduced after applying corrections, achieving the repeated error correction of surface code for the first time. This experiment represents a fully functional instance of an error-correcting surface code, providing a key step on the path towards scalable fault-tolerant quantum computing.

Periodically driven systems, or Floquet systems, exhibit many novel dynamics and interesting out-of-equilibrium phases of matter. Those phases arising with the quantum systems' symmetries, such as global $U(1)$ symmetry, can even show dynamical stability with symmetry-protection. Here we experimentally demonstrate a $U(1)$ symmetry-protected prethermal phase, via performing a digital-analog quantum simulation on a superconducting quantum processor. The dynamical stability of this phase is revealed by its robustness against external perturbations. We also find that the spin glass order parameter in this phase is stabilized by the interaction between the spins. Our work reveals a promising prospect in discovering emergent quantum dynamical phases with digital-analog quantum simulators., 14 pages, 4 figures, and supplementary materials

Scaling up to a large number of qubits with high-precision control is essential in the demonstrations of quantum computational advantage to exponentially outpace the classical hardware and algorithmic improvements. Here, we develop a two-dimensional programmable superconducting quantum processor, Zuchongzhi, which is composed of 66 functional qubits in a tunable coupling architecture. To characterize the performance of the whole system, we perform random quantum circuits sampling for benchmarking, up to a system size of 56 qubits and 20 cycles. The computational cost of the classical simulation of this task is estimated to be 2-3 orders of magnitude higher than the previous work on 53-qubit Sycamore processor [Nature 574, 505 (2019)NATUAS0028-083610.1038/s41586-019-1666-5. We estimate that the sampling task finished by Zuchongzhi in about 1.2 h will take the most powerful supercomputer at least 8 yr. Our work establishes an unambiguous quantum computational advantage that is infeasible for classical computation in a reasonable amount of time. The high-precision and programmable quantum computing platform opens a new door to explore novel many-body phenomena and implement complex quantum algorithms.

Quantum resetting protocols allow a quantum system to be sent to a state in the past by making it interact with quantum probes when neither the free evolution of the system nor the interaction is controlled. We experimentally verify the simplest non-trivial case of a quantum resetting protocol, known as the $\mathcal{W}_4$ protocol, with five superconducting qubits, testing it with different types of free evolutions and target-probe interactions. After projection, we obtained a reset state fidelity as high as $0.951$, and the process fidelity was found to be $0.792$. We also implemented 100 randomly-chosen interactions and demonstrated an average success probability of $0.323$ for $|1\rangle$ and $0.292$ for $|-\rangle$, experimentally confirmed the nonzero probability of success for unknown interactions; the numerical simulated values are about $0.3$. Our experiment shows that the simplest quantum resetting protocol can be implemented with current technologies, making such protocols a valuable tool in the eternal fight against unwanted evolution in quantum systems., 9 pages, 6 figures, 1 table + Supplementary Materials

Superconducting quantum computers (SQC) can solve some specific problems which are deeply believed to be intractable for classical computers. The control and measurement of qubits can't go on without the synchronous operation of digital-to-analog converters (DAC) array and the controlled sampling of analog-to-digital converters (ADC). In this paper, a scalable self-adaptive synchronous triggering system is proposed to ensure the synchronized operation of multiple qubits. The skew of the control signal between different qubits is less than 25 ps. After upgrading the clock design, the 250 MHz single-tone phase noise of DAC has been increased about 15 dB. The phase noise of the 6.25 GHz qubit control signal has an improvement of about 6 dB., 5 pages, 12 figures, IEEE Real Time Conference

Superconducting quantum processors are manufactured based on a semiconductor process, which makes qubit integration possible. At the same time, this kind of qubit exhibits high-performance fidelity and decoherence time and requires a programmable arbitrary waveform generator (AWG). This paper presents the implementation of an AWG with a sampling rate of two-gigabit samples per second as well as 16-bit vertical resolution digital-to-analog converters. The AWGs are designed for a scaled-up usage scenario by integrating them with separate microwave devices onto a single backplane. A special waveform sequence output controller is designed to realize seamless waveform switching and arbitrary waveform generation. The jitter of multiple AWG channels is around 10 ps, and the integral nonlinearity and differential nonlinearity are both about 2 least significant bits. This customizable AWG has been used in several superconducting quantum processors, and the result of multiple qubits’ measurement verifies that the AWG is qualified for controlling tens of superconducting qubits.Superconducting quantum processors are manufactured based on a semiconductor process, which makes qubit integration possible. At the same time, this kind of qubit exhibits high-performance fidelity and decoherence time and requires a programmable arbitrary waveform generator (AWG). This paper presents the implementation of an AWG with a sampling rate of two-gigabit samples per second as well as 16-bit vertical resolution digital-to-analog converters. The AWGs are designed for a scaled-up usage scenario by integrating them with separate microwave devices onto a single backplane. A special waveform sequence output controller is designed to realize seamless waveform switching and arbitrary waveform generation. The jitter of multiple AWG channels is around 10 ps, and the integral nonlinearity and differential nonlinearity are both about 2 least significant bits. This customizable AWG has been used in several superconducting quantum processors, and the result of multiple qubits’ measurement verifies that the A...

An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper., 4 pages, 6 figures and 1 table, Submitted to 'Chinese Physics C'

A very Sensitive Neutron Spectrometer (SNS) is designed for SG-III prototype laser facility in China. The spectrometer consists of a 960 channel single-neutron-interaction detector array placed 16.67m from the Inertial Confinement Fusion (ICF) target. Each detector channel has a plastic scintillator coupled to a photomultiplier tube followed by a discriminator, shaper, TDC and ADC to allow the measurement of neutron arrival time as well as pulse amplitude. The array is capable of measuring yields as low as 4¥10 5 neutrons (100 detected hits) with resolution of1.0 ns (90keV for 14-MeV neutrons with 16.67m flight path). Details of design and testing will be presented.

We present a data acquisition (DAQ) system for a three slender 3 He Position-Sensitive Proportional Counters (PSPC) based neutron dosimeter. The DAQ system measures the charge of the neutron-induced events, calculates the position of the events, and provides the power supply for the dosimeter. The DAQ system provides a significant support for the proof of principle.