Search

A class of vertical 1700 V 4H-silicon carbide (SiC) semi-superjunction (SJ) Schottky diodes have been simulated and optimized to ensure practical and cost-effective realization. The proposed structures could be realized using an n-type drift region of 9- μm and etching trenches partway through this region to form the required mesa regions. P-pillars are then created through implantation into both the trench sidewalls and trench bottom. This semi-SJ topology overcomes problems with conventional SJs that span the full drift region (full-SJs), namely a narrow charge-balance window required to achieve the maximum VBD , and hard, snappy, switching characteristics. The optimized SiC semi-SJ comprises a 7- μm SJ region above 2- μm of conventional drift region. An angled trench sidewall ( α ), 10° off vertical, introduces a graded charge profile throughout the n-pillar, which widens the implantation window by 34%, while maintaining a VBD of ~2.1 kV and a RON,SP comparable to a vertical full-SJ. Further advantages of the proposed semi-SJ, over a full-SJ, include a reduced trench aspect ratio and two orders of magnitude lower leakage current. Furthermore, the graded charge profile in the n-pillar gradually depletes the drift region, suppressing ringing and reducing the peak reverse recovery current by 50%.

A class of vertical 1700-V 4H-SiC superjunction (SJ) Schottky diodes have been simulated and optimized, producing results that are below the unipolar limit, while also ensuring practical and costeffective realization. A conventional vertical SJ is obtained in T-CAD software, using an n-type drift region of 9- $\mu \text{m}$ and etching trenches through this region to the substrate to leave isolated mesa structures. P-columns are then created through implantation into the trench sidewalls. The charge-balanced SJ diode maximizes the breakdown voltage ( ${V}_{\text {BD}}$ ) and minimizes the specific ON-resistance ( ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ ). However, a narrow implantation window would make the vertical structure hard to fabricate. Therefore, by introducing an angled trench sidewall ( $\alpha $ ), 10° off vertical, a graded charge profile is introduced reducing ${V}_{\text {BD}}$ by 2.5% and increasing ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ by 9%. However, the implantation window is widened by 20% compared with the vertical device, making the successful production of the devices more likely. To rebalance the 10° structure, a 1- $\mu \text{m}$ region of increased n-type doping is introduced at the top of the n-pillar. This partially recovers the lost ${V}_{\text {BD}}$ and ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ while maintaining an implantation window wider than the vertical SJ. The balance between ${R}_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ and implantation window can be tuned depending on the doping of the 1- $\mu \text{m}$ top region. The 10° structure can also be rebalanced by introducing a second 4- $\mu \text{m}$ region of intermediate n-type doping, underneath the 1- $\mu \text{m}$ surface region. This recovers $R_{{\mathrm{\scriptstyle{ON}}},\text {SP}}$ , while maintaining an implantation window that is 7% wider.

This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09 × 105 cm−2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing D IT levels of 3.3 × 1011 cm−2 eV−1 at E C−E T = 0.2 eV. The homo-epitaxially grown 3C-SiC material’s suitability for MOS applications could also be confirmed by leakage current measurements.

This letter reports on the improvement of a SiO2 layer formed by atomic layer deposition on 4H-SiC, using a post-deposition anneal in forming gas ambient. Capacitance–voltage measurements revealed good electrical properties, compared to a thermal oxide which was grown in N 2 O, with flatband voltage values averaging at -0.29 V and a low positive mobile ion charge density in the order of 1010 cm−2. XPS analysis revealed the FG annealed sample to have the most Si rich interface comparatively to other PDAs, with a C:Si ratio of 0.72, allowing more Si bonds to be terminated. SIMS analysis identified an increase in hydrogen near the interface of the FG-annealed sample with a peak concentration of 2.12 × 1021 cm−3. It is concluded that the improvement in electrical performance is due to the hydrogen passivating trap states at the SiO2/4H-SiC interface.