Search

The reliability results of floating-gate (FG) memory using 5-nm tunnel oxides in mature to advanced logic processes from multiple foundries are described. The studies have shown that it is possible to develop a small-bit-count FG nonvolatile memory (NVM) array by using 5-nm oxide, which has enabled embedded logic NVM in advanced CMOS processes with no additional masks or processing steps.

An all optical method has been proposed for quantum Hadamard gate implementation. This quantum gate was realized by using Y-junction beam splitter. Normal modes in waveguides have been used as quantum bit. This all optical gate can be used in quantum computation and communication. The proposed Hadamard gate has potential of being more compact and easily realized compared to other optical implementations. By using planar lightwave circuit in implementation, the width of Y-junction input waveguide, width of each branch, angle of bend and length of bend were obtained 1 micron, 0.75 micron, 45[degrees] and 0.75 micron, respectively. By using planar lightwave circuit in implementation, the radius of large air holes and the radius of small holes were obtained 0.2 ands 0.1 micron, respectively. The index of substrate was 1.325. Implementation based on photonic crystal structures and planar lightwave circuit technology was used in integrated optics Key words: Quantum gate, quantum communication, quantum computation, qubit, integrated optics, INTRODUCTION Quantum gates are important part of quantum communication and computation. Many researchers work on theories of quantum computation, such as entanglement, quantum decoherernce, quantum cryptography and quantum error correction. [...]

The aim of this study was to quantify image noise and signal recovery in respiratory gated PET. A Jaszczak phantom filled with [sup.18]F was placed on a custom built motion platform. Different source to background activity ratios were used. An Anzai belt, a surface tension monitoring device, was strapped around the phantom to track the motion and to trigger the gated PET cycle. Data were acquired into 12 bins throughout one gating cycle. The binned data were also summed to produce image sets representing acquisitions with different numbers of gates, including a non-gated image set. The image noise was estimated using the bootstrap method. Images were generated from 100 sinogram replicates and reconstructed using ordered subsets-expectation maximization (OSEM), 4 iterations and 8 subsets. From the reconstructed image replicates, mean and standard deviation images were created, from which the average image signal-to-noise ratio (SNR) and contrast-to-noise ratio (CNR) of each sphere were calculated. The SNR and CNR were evaluated as a function of the number of gates. The SNR and CNR result in the expected Poisson limited correlation with the number of gates for the larger lesions. Because of the motion, the CNR calculated from the images produced with no or few gates is nearly a factor of 2 less than the expected value for the 3 smallest spheres. As the number of gates increases, the CNR correlates with the expected values. Beyond 6 gates, image noise dominates over any signal improvement, which is reflected in the low CNR values of the smallest spheres. The results of this study show that gating can provide improvement in signal recovery with minimal loss of CNR for small, moving lesions. Index Terms--Gating, image noise, PET, respiratory motion.

Performance of multichannel lateral insulated gate bipolar transistors (MC-LIGBTs) fabricated in a cost-effective, fully implanted, CDMOS-compatible process in junction isolation technology is reported. It is shown that combining the MC and the SA-segmented N (super +)P/P(super +) [NPN] anode concepts creates a device that exhibits both low on-state and turnoff losses and is best placed for use in power IC applications.

The Lambert function-based analytic solution for the surface potential of undoped-body single gate bulk MOSFETs is extended to offer an explicit analytic solution of the surface potential of undoped-body symmetric dual-gate devices. The error produced by the proposed solution compared to exact results is small for typical device dimensions and bias conditions.

The analysis of the leakage power and input pattern dependence o leakage for extremely scaled double-gate circuits is presented, comparing with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications.

The effects of preamorphization implantation (PAI) on the interface properties between hafnium-silicate (HfSiO) gate dielectrics and silicon substrates were examined. It was found that in the case of an NH3 nitrided interface, the PAI could improve the interface trap density [D(sub IT)] compared with the no PAI case.

Strong polarity dependent charge trapping effects have been observed in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current-voltage (I-V) and capacitance-voltage (C-V) sensing techniques. The polarity dependent charging effects are explained in terms of the difference in barrier height for substrate and gate injection and of the inherent asymmetry of the dual layer gate dielectric.

The performance of a lateral p-n junction quantum well edge emitting laser transistor with an extra gate contact is studied. The incorporation of the gate contact provides an opportunity to control the threshold current and output optical power by the gate voltage.

A study was conducted to experimentally evaluate the input-output surface for a biochemical AND gate. The results showed that under optimized conditions, the biochemical gates could be concatenated for up to order 10 processing steps that could be applied to advance scalable biochemical computing.

The operation phase diagrams of all-metallic submicrometer ferromagnetic NOT-gate devices are presented. It is demonstrated how changing the NOT-gate orientation to an applied field affects the operating phase diagram and may assist the integration of NOT-gates with other types of junction to realize a full magnetic logic scheme.

Byline: E. Badreddin Analogical gates are developed to implement four-quadrant fuzzy-generalisation of Boolean logical gates. They provide an alternative to the traditional rule-based realisation of fuzzy inference. Therefore, analogical gates can be used in a wide range of applications especially for multi-criteria aggregation. In this paper, the basic properties of the analogical gates are reviewed, their advantages compared to the traditional fuzzy formalism are discussed and some preliminary results on synthesis are elaborated. To demonstrate their benefits, analogical gates are applied in the risk assessment of twenty industrial plants for insurance purposes. The results are compared to those made by human experts and are found to match their assessments with a good accuracy.

A NIST researcher recently completed a theoretical analysis of errors in a seven-junction electron pump in the presence of a source of high-frequency photons. The electron pump is a critical […]