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Water is the most essential element for human life after air, hence the amount and quality of water resources must be monitored by the appropriate government agencies. The goal of this research is to create and implement an IoT‐based rivers monitoring prototype system. Two basic components make up the proposed system: the first component represents the node points, and the second component represents the control point. In order to achieve continuous updates of the information via Internet from the node side, ESP32 with its built‐in Wi‐Fi adapter was utilized. The node should pinpoint three major situations, Normal, High. and Low of river water, and then transfer it using IoT to the control point to take an action depending on conditions at the river. © 2023 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

This effort develops and uses a smart stick to help blind individuals walk more safely and avoid hazards. This research paper involved to develop smart stick for blind people to help them to walk safely by avoiding obstructions, and at emergency conditions sent their location to person in charge like a doctor or relatives to help them accordingly. Three ultrasonic sensors are used in the proposed device’s architecture to detect obstructions at three different heights, low, mid, and high obstructions using speaker to alert the blind person. An emergency message with the location of the blind person’s phone is sent through a mobile app to the doctor or person in charge whenever the designed smart stick’s emergency button is touched, or the stick is dropped down. The Arduino Uno platform, Bluetooth model, MPU-6050 3-axis gyroscope as a position sensor, and microSd card module has been used to effectively implement the stick. At the testing stage, the device gave good results. The user received notifications in the form of voice messages and vibrations from the smart stick when it detects things or obstacles in front of them. Additionally, even though they cannot directly activate it, the automated emergency condition has been detection and activated. [ABSTRACT FROM AUTHOR]

The goal of this research article is to build and implement a low-cost, user-friendly 74-series logic integrated circuits (ICs) tester that is independent of a computer. Depending on the truth table of the gates and the IC configuration, the logic IC tester will be able to test the operation of the 74 series logic gates (AND, OR, NOR, NAND, XOR) of those ICs. It is feasible to test a range of logic ICs with higher pin widths thanks to the proposed system’s usage of an Arduino Mega platform module as a microcontroller, which provides the ability to connect 54 programmed logic inputs or outputs. The versatility offered by this design and the use of a personal computer allow for the reprograming and updating of the logic IC functional tester. Any 74-series ICs testing outcome will be shown on liquid crystal display (LCD) at the gate level. The logic IC functional tester was successfully constructed and operates flawlessly. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method to adaptively select the best driver to load transistor fin ratio of CMOS FinFET logic inverter according to the best values of noise margins and inflection voltage with a comparison of the use of different and combined Si and Ge as a load and/or driver semiconductor channel in CMOS FinFET inverter logic circuit. The methodology of optimizing the driver to load transistor fin ratio depends strongly on improving the noise margins and inflection voltage of the output characteristics of CMOS logic inverter. The first step in this investigation of CMOS-FinFET-inverter is to obtain the output characteristics (Id-Vd) of the FinFET, and then use the MATLAB simulation model to create CMOS Fin- FET transfer characteristics. Transfer characteristics of CMOS-FinFET-logic inverter are studied with fin ratios Np/Nn of 5/1, 4/1, 3/1,2/1, 1/1, 1/2, 1/3, 1/4, 1/5. Noise margins and inflection voltage are used as critical factors to obtain the optimal fin ratio (Np/Nn). The results indicate that optimization depends strongly on the fin ratio for all combined semiconductor loads to FinFET driver inverters. The results show that the best ratios for Si:Si, Si:Ge, Ge:Si, and G:Ge are 2:1, 1:4, 2:1, and 1:3 respectively. [ABSTRACT FROM AUTHOR]

This research paper is to define new rule to find the divisibility of stream of binary on any prime numbers 3, 5, 7 ...... with reminder 0. In general, the divisibility of binary numbers is most important in many digital circuits and mathematical applications. This paper explains this new rule for evaluating the divisibility of any binary number on any prime number greater than 2. This rule will depend on separating the binary number into blocks of bits then processes each block separately in a special procedure to find the possible divisibility on the prime number. After testing this new rule with prime numbers 3, 5, and 7 as a sample of prime numbers, the finding shows that this rule provides fast and true results. [ABSTRACT FROM AUTHOR]

This study presents the model, design, and construction of the Arduino based robotic arm, which functions across a distance as it is controlled through a mobile application. A six degree of freedom robotic arm has been designed and implemented for the purpose of this research. The design controlled by the Arduino platform receives orders from the user’s mobile application through wireless controlling signals, that is Bluetooth. The arm is made up of five rotary joints and an end effector, where rotary motion is provided by the servomotor. Each link has been first designed using solid works and then printed by 3D printer. The assembly of the parts of the robot and the motor’s mechanical shapes produce the final prototype of the arm. The Arduino has been programmed to provide rotation to each corresponding servo motor to the sliders in the designed mobile application for usage from distance. [ABSTRACT FROM AUTHOR]

This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (WF=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics. [ABSTRACT FROM AUTHOR]

This paper represents the impact of nanowires ratio of silicon nanowire transistors on the characteristics of 6-transistors SRAM cell. This study is the first to demonstrate nanowires ratio optimization of Nano-scale SiNWT Based SRAM Cell. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both nanowires ratio and digital voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decreasing in optimization ratio but with increasing in current and power. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower dimensions and lower inflection currents and then with lower power consumption.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier’s specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18-μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation. [ABSTRACT FROM AUTHOR]

This brief presents an adjustable third-order filter without employing passive elements. The proposed filter combines two low-pass and band-pass MOSFET-only topologies to configure a dual-output structure, while the transconductances and parasitic gate-source capacitances of the transistors act as the required passive elements. The main core of the proposed filter contains just 3 transistors that with the elimination of passive elements results in a small silicon area and low power consumption. The proposed filter benefits from low-input and high-output impedances that is an advantage for cascading in current-mode systems. Moreover, a kind of self-biasing topology is used to configure the proposed filter in which a control voltage is provided to move the center frequency of both outputs in a wide frequency range. The proposed circuit was fabricated using TSMC 0.18 μm CMOS process. Experimental and simulation results at a supply voltage of 1.8 V show a bandwidth range from 38.1 MHz to 99.5 MHz for a capacitive load bigger than 15 pF, while the average power consumption is 435 μW. It occupies a silicon area of just 43 μm × 86 μm. [ABSTRACT FROM AUTHOR]

This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics. [ABSTRACT FROM AUTHOR]

This paper shows the temperature sensitivity of FinFET and the possibility of using FinFET as a temperature nano sensor based on Fin width of transistor. The multi-gate field effect transistor (MuGFET) simulation tool is used to examine the temperature effect on FinFET characteristics. Current-voltage characteristics with various temperatures and channel Fin width (WF = 5,10,20,40 and 80 nm) are at first simulated, the diode mode connection has been used in this study. The best temperature sensitivity of the FinFET is has been considered under the biggest ΔI at the working voltage VDD with range of 0–5 V. According to the results, the temperature sensitivity increased linearly with all the range of channel Fin width (5-80 nm), also, the lower gate Fin width (WF=5nm) with higher sensitivity can achieved with lower working voltage (VDD=1.25 V). [ABSTRACT FROM AUTHOR]

This paper reviews the fabrication technologies of silicon nanowire transistors (SiNWTs) and rapidly development in this area, as this paper presents various types of SiNWT structures, development of SiNWT properties and different applications until nowadays. This research provides a good comparison among fabrication technologies of SiNWTs depending on a new factor DIF, this factor depends on the size of channel and power consumption in channel. As a result of this comparison, the best technology to use in the future to fabricate silicon nano transistors for future ICs is AFM nanolithography. [ABSTRACT FROM AUTHOR]

The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET's designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 πS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general. [ABSTRACT FROM AUTHOR]

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4. [ABSTRACT FROM AUTHOR]

This paper presents the temperature-gate oxide thickness characteristics of a fin field-effect transistor (FinFET) and discusses the possibility of using such a transistor as a temperature nano-sensor. The investigation of channel oxide thickness-based temperature characteristics is useful to optimized electrical and temperature characteristics of FinFET. Current-voltage characteristics with different temperatures and gate oxide thickness values (Tox=1, 2, 3, 4, and 5 nm) are initially simulated, and the diode mode connection is considered to measure FinFET's temperature sensitivity. Finding the best temperature sensitivity of FinFET is based on the largest change in current (ΔI) within a working voltage range of 0-5 V. According to the results, the temperature sensitivity of FinFET increases linearly with oxide thickness within the range of 1-5 nm, furthermore, the threshold voltage and drain-induced barrier lowering increase with increasing oxide thickness. Also, the subthreshold swing (SS) is close to the ideal value at the minimum oxide thickness (1 nm) then increases and diverges with increasing oxide thickness. So, the best oxide thickness (nearest SS value to the ideal one) of FinFET under the conditions described in this research is 1 nm. [ABSTRACT FROM AUTHOR]

In this paper, we present the impact of downscaling of nano-channel dimensions of Indium Arsenide Fin Feld Effect Transistor (InAs-FinFET) on electrical characteristics of the transistor, in particular; (i) ION/IOFF ratio, (ii) Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to simulate and compare the considered characteristics based on variable channel dimensions: length, width and oxide thickness. The results demonstrate that the best performance of InAs-FinFET was achieved with channel length = 25 nm, width=5 nm, and oxide thickness between 1.5 to 2.5 nm according to the selected scaling factor (K = 0.125). [ABSTRACT FROM AUTHOR]

Among various sensing and monitoring techniques, sensors based on field effect transistors (FETs) have attracted considerable attention from both industry and academia. Owing to their unique characteristics such as small size, light weight, low cost, flexibility, fast response, stability, and ability for further downscaling, silicon nanowire field effect transistor (SiNW-FET) can serve as an ideal nanosensor. It is the most likely successor to FET-based nanoscale devices. However, as the dimensions (channel length and diameter) of SiNWT channel are shrinking down, electrical and temperature characteristics of SiNWTs should be affected, thereby degrading transistor performance. Although applications of SiNWTs as biological and/or chemical sensors have been extensively explored in the literature, less attention has been devoted to utilize such transistors as temperature sensors. Therefore, this paper characterizes the temperature sensitivity of SiNWT depending on the channel oxide thickness and also presents the possibility of using it as a nano-temperature sensor. The MuGFET simulation tool was used to investigate temperature characteristics of the nanowire. Current-voltage characteristics with different values of temperature and with different thickness of the nanowire gate (oxide thickness (TOX) = 1, 2, 3, 4, and 5 nm), were simulated. Metaloxide- semiconductor (MOS) diode mode connection was suggested for measuring the temperature sensitivity of SiNWT. Several operating voltages (0.25 to 5 V) with various working temperature (250 to 450 K) were investigated. The obtained results show that the highest temperature sensitivity was achieved by increasing oxide thickness to 5 nm. The impact of the considered temperature on SiNWT characteristics demonstrates the possibility of utilizing it as a temperature nanosensor. [ABSTRACT FROM AUTHOR]

Nano-electronic applications have benefited enormously from the great advancement in the emerging Nano-technology industry. The tremendous downscaling of the transistors’ dimensions has enabled the placement of over 100 million transistors on a single chip thus reduced cost, increased functionality and enhanced performance of integrated circuits (ICs). However, reducing size of the conventional planar transistors would be exceptionally challenging due to leakages electrostatics and other fabrication issues. Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate and a successor to conventional planar devices in nanoscale technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest of researchers in both academia and industry. However, aggressively scaling down of channel dimensions, will degrade the overall performance due to detrimental short channel effects. In this paper, we investigate the impact of downscaling of nano-channel dimensions of Germanium Fin Feld Effect Transistor (Ge-FinFET) on electrical characteristics of the transistor, namely; ION/IOFF ratio, Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to conduct a simulation study to achieve optimal channel dimensions by considering channel length (L), width (W), and oxide thickness (TOX) individually. In addition, the effects of simultaneous consideration of all dimensions by exploiting a scaling factor, K was evaluated. According to the obtained simulation results, the best performance of Ge-FinFET was achieved at a minimal scaling factor, K = 0.25 with 5 nm channel length, 2.5 nm width, and 0.625 nm oxide thickness. [ABSTRACT FROM AUTHOR]

The characteristics of nanowire (NW) inverters with three types of circuit configurations were simulated and studied. The MuGFET simulation tool was used to produce the output characteristics of N- and P-channel NW transistors. The model presented in the present study utilized these output characteristics of NW transistors as input to the MATLAB program to calculate the static characteristics of each inverter. The results show different characteristics for the advantages and disadvantages of each circuit inverter; the NW-CMOS and the NW-NMOS circuits are found to the best circuit inverters based on logic level and noise margins. [ABSTRACT FROM AUTHOR]

This paper presents the temperature characteristics of a silicon nanowire transistor and its use as a temperature sensor. The OMEN nanowire simulation tool was used to investigate the temperature characteristics of the transistor. Current-voltage characteristics with different values of temperature for three orientations were simulated. The metal-oxide-semiconductor (MOS) diode connection suggests the use of the silicon nanowire transistor as a temperature nanosensor. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]

This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20-1000 KΩ with Vdd = 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100-200 KΩ.

This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (V dd optimizations of nanoscale SiNWT-based SRAM cell. Noise margins and inflection voltage of butterfly characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on nanowire dimensions and V dd. The increase in V dd from 1 V to 3 V tends to decrease the dimensions of the optimized nanowires but increases the current and power. SRAM using nanowire transistors must use V dd of 2 or 2.5 V to produce SRAM with lower dimensions, inflection currents, and power consumption.

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.

This study is the first to demonstrate characteristics optimization of nanowire resistance load inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on resistance value. Increasing of load resistor tends to increasing in noise margins until saturation point, increasing load resistor after this point will not improve noise margins significantly.

This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter optimization reveals that when Vdd increases, the optimized value of (Dp/Dn) decreases. Channel length optimization results show that when Vdd increases, the optimized value of Ln decreases and that of (Lp/Ln) increases. Dimension ratio optimization reveals that when Vdd increases, the optimized value of Kp/Kn decreases, and silicon nanowire transistor with suitable dimensions (higher Dp and Ln with lower Lp and Dn) can be fabricated.

This paper presents the temperature characteristics of silicon nanowire transistors (SiNWTs) and examines the effect of temperature on transfer characteristics, threshold voltage, I(ON)/I(OFF) ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The (MuGFET) simulation tool was used to investigate the temperature characteristics of a transistor. The findings reveal the negative effect of higher working temperature on the use of SiNWTs in electronic circuits, such as digital circuits and amplifiers circuits, because of the lower I(ON)/I(OFF) ratio, higher DIBL, and higher SS at higher temperature. Moreover, the ON state is the optimum condition for using a transistor as a temperature nano-sensor.

This paper shows the effect of the dimensions of nanowires on threshold voltage, ON/OFF current ratio, and sub-threshold slope. These parameters are critical factors of the characteristics of silicon nanowire transistors. The MuGFET simulation tool was used to investigate the characteristics of a transistor. Current-voltage characteristics with different dimensions were simulated. Results show that long nanowires with low diameter and oxide thickness tend to have the best transistor characteristics.