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In this study, a two-dimensional electron gas (2DEG), which is a conductive layer formed at the interface of Al2O3 and TiO2, was used as an electrode for resistive random access memory (RRAM) and implemented in a cell size down to 30 nm. For an RRAM device comprising W/2DEG/TiO2/W, we confirmed that the dominant switching mechanism changed from interfacial to filamentary as the cell size decreased from 500 nm to 30 nm. Through analyses of changes in forming characteristics and conduction mechanisms in the low resistive state depending on the cell size, it was identified that the 2DEG acted as an oxygen-scavenging layer of TiO2 during the resistive switching process. By comparing the switching characteristics of RRAM devices with and without 2DEG for a 30 nm cell size, we confirmed that a high-performance 2DEG RRAM was realized, with highly uniform current–voltage characteristics, a low operating voltage (∼1 V), and a high on/off ratio (>102). Finally, the applicability of the proposed device to a crossbar array was validated by evaluating 1S1R operation with an NbO2-based selector. Considering the improved switching uniformity, the 2DEG RRAM shows promise for high-density memory applications. [ABSTRACT FROM AUTHOR]

HfxZr1-xO2 thin films exhibit a high dielectric constant at the morphotropic phase boundary (MPB), which is beneficial for high-k dielectric applications. To minimize the equivalent oxide thickness, the effects of various HZO thicknesses and compositions on the MPB were investigated. In general, HZO films with a thickness of 10 nm exhibit a high dielectric constant owing to MPB at a composition of Hf:Zr = 3:7. However, it was confirmed that composition optimization is required for HZO films with thicknesses below 10 nm to achieve an MPB. As the HZO thickness decreases, a low Zr ratio is favorable for achieving a high dielectric constant (>45) by MPB, which is expected to be due to the large impact of the interface that consequently induces a change in phase formation. Results of electrical and x-ray diffraction analyses confirmed that a high dielectric constant was obtained when the ratio of the tetragonal phase increased and that the tetragonal phase was well formed at a low Zr ratio in the 6 nm-thick HZO film. Therefore, the optimal ratio between the tetragonal and orthorhombic phases should be determined to achieve MPB in HZO thin films, and this can be achieved by composition optimization. [ABSTRACT FROM AUTHOR]

Ion‐based electrochemical random‐access memory (ECRAM) is proposed for synaptic applications owing to its promising characteristics that have the potential to accelerate data processing through neuromorphic systems. However, attaining ideal synaptic functionalities and constructing high‐density vertical synapse arrays are challenging due to issues related to uncontrolled ion migration and constraints in 3D multi‐stacking. Here, a breakthrough using 3D stackable Li ion‐based vertical‐sensing ECRAM (VS‐ECRAM) is presented with an ion‐permeable ultrathin WS2 electrode synthesized through low‐temperature (200 °C) atmospheric‐pressure plasma‐enhanced chemical vapor deposition (AP‐PECVD). The direct AP‐PECVD of the WOx channel layer induces WS2 formation in the surface region, which exhibits sufficient electrical conductivity to function as an electrode. By utilizing the WS2 electrode as an ion‐barrier layer in the VS‐ECRAM synapse, excellent weight update linearity and cycling variability are achieved due to the finely controlled ion migration. Furthermore, a two‐layer stacked 3D VS‐ECRAM is successfully fabricated through the vertical WS2 formation, and independent weight updates without any disturbance are confirmed. Finally, a high pattern recognition accuracy of 95.22% is obtained using a multi‐layer perceptron‐based neural network. Therefore, the proposed 3D stackable WS2‐based VS‐ECRAM exhibits a strong potential for application in high‐density neuromorphic devices with excellent synaptic performances. [ABSTRACT FROM AUTHOR]

In the age of the Internet of Things, the proliferation of edge devices has resulted in a significant increase in personal information that is susceptible to theft and counterfeiting at various stages of data communication. As a result, substantial attention has been focused on hardware (HW) security elements, such as the true random number generator and physical unclonable function. With the recent surge in research and development of emerging memristors, which exploit the inherent variability of these devices, there has been a notable increase in studies on HW security. Particularly, volatile threshold switch (TS) devices, which exhibit insulator/metal characteristics below/above a certain threshold voltage, show great promise as security devices due to their lower power consumption and higher cycling endurance compared to nonvolatile memory devices. Despite the promising attributes and increasing demand for TS devices for HW security, there remains a lack of a comprehensive overview covering various TS devices and their potential contributions to HW privacy. To address this gap, this review provides an encompassing analysis of different types of TS devices and their performance in HW security literature, providing insight into current limitations and the future prospects of HW security primitives based on TS devices. [ABSTRACT FROM AUTHOR]

In this study, we investigated the influence of ultraviolet (UV) treatment on the ovonic threshold switch (OTS) to improve its selector properties. Our findings demonstrate that iteratively applying UV treatment during the film deposition phase considerably improves device characteristics compared to a single UV treatment. Consequently, this process provided a significant decrease in the forming voltage, maintaining outstanding switching features, with an off-state current of approximately 2 nA. Furthermore, the refined UV treatment process resulted in an impressive 45% improvement in threshold voltage drift characteristics and facilitated excellent switching uniformity. X-ray photoelectron spectroscopy analysis revealed alterations in the bonding structure of the Si–Te–As–Ge film after UV exposure. Specifically, a transition was observed from unstable homopolar bonds, such as As-As or Te–Te, to their more stable heteropolar equivalents, such as As–Te. These results highlight the potential of UV treatment as an effective method for enhancing the OTS performance. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS2), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS2 transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS2 transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm2/V·s), on/off current ratio (from 4.90 × 105 to 1.52 × 107), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS2 transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS2 transistor array. [ABSTRACT FROM AUTHOR]

Defects are essential to switch the resistance states in resistive random-access memory (RRAM) devices. Controlled defects in such devices can lead to the stabilization of the switching performance, which is useful for high-density memory and neuromorphic computing applications. In contrast, uncontrolled defects in RRAM can generate randomness and increase intrinsic entropy, which are useful for security applications. In this tutorial, we explain how to engineer defects in RRAM devices. More specifically, we focus on defect engineering of the oxide layer and how the defects can affect the switching mechanism. Defect engineering processes include the doping effect, nanocrystal-based switching layer design, embedded metals in switching oxide, defective electrode design, etc. We explain how defects can improve the electrical performance of RRAM devices and the recent development of applications using defect-based RRAM devices. [ABSTRACT FROM AUTHOR]

This study investigated the impact of a Ge2Sb2Te5 (GST) thermal barrier on the performance of NbO2-based selector devices. Our findings showed that the GST barrier could significantly decrease the off-state leakage current from 3 μA to 300 nA without increasing the threshold switching voltage owing to its insulation properties and high thermal resistance. We also found that the GST barrier can effectively contain the Joule heat within the NbO2 switching region, as confirmed through a cryogenic analysis of the thermal resistance of GST. The results showed that the GST/NbO2 device had a thermal resistance 3.48 times higher than that of a single-layer NbO2 device. Our results provide design guidelines for utilizing a barrier layer to reduce the leakage current in low-power threshold switching devices. [ABSTRACT FROM AUTHOR]

To maximize the multilevel data storage capability for high-density memory applications, precise control of quantized conduction with ultralow transition energy is required. We report the quantized conduction in Ag/Ag2S/vacuum conductive-bridge random access memory under various pulse conditions to regulate atomic motion at room temperature. Using stochastic analysis, we unveil a pulse condition for supplying the optimal energy that allows precise atom detachment and has a high dissolution probability. In addition, we calculate the transition energy required to change each quantized state for an Al2O3 electrolyte and vacuum gap. We determine a large transition energy of Ag in Al2O3 (8–1 mJ), hindering the precise control of quantized conduction, whereas the transition energy of Ag in vacuum is relatively low (397–95 nJ), enabling proper atomic motion. [ABSTRACT FROM AUTHOR]

Neuromorphic computation is one of the axes of parallel distributed processing, and memristor-based synaptic weight is considered as a key component of this type of computation. However, the material properties of memristors, including material related physics, are not yet matured. In parallel with memristors, CMOS based Graphics Processing Unit, Field Programmable Gate Array, and Application Specific Integrated Circuit are also being developed as dedicated artificial intelligence (AI) chips for fast computation. Therefore, it is necessary to analyze the competitiveness of the memristor-based neuromorphic device in order to position the memristor in the appropriate position of the future AI ecosystem. In this article, the status of memristor-based neuromorphic computation was analyzed on the basis of papers and patents to identify the competitiveness of the memristor properties by reviewing industrial trends and academic pursuits. In addition, material issues and challenges are discussed for implementing the memristor-based neural processor. [ABSTRACT FROM AUTHOR]

To improve the endurance and polarization switching speed of Hf1âˆ' x Zr x O2 (HZO) ferroelectric films, we designed a 10 nm Hf0.5Zr0.5O2 + ZrO2 (HZZ) nanolaminate structure. Three films with different ZrO2 interlayers thicknesses were compared to find the optimal condition to implement the effect of the topological domain wall which was proposed recently. The HZZ film were deposited by repeatedly stacking ten HZO (∼0.92 nm) and six ZrO2 (∼0.53 nm) layers; they exhibited a dramatic reduction of coercive field without an effective loss of remnant polarization. The endurance at operation voltage increased by more than 100 times compared with that of the solid solution HZO film, and the switching speed was increased by more than two times. The formation of the tetragonal phase-like spacer between the ferroelectric polar regions appears to be the main factor associated with the reduction of the switching barrier and leads to the acceleration of the switching propagation over multiple domains. [ABSTRACT FROM AUTHOR]

Conductance variations of resistive random-access memory (RRAM) are significant challenges that hinder the accurate inference of neural network (NN) hardware. In this study, we exploit the read noise of the RRAM as an active computational enabler for implementing probabilistic NN. As electrical characteristics of RRAM are directly related to the properties of conductive filament (CF), we statistically explore read current of TiOx-based RRAM with different forming conditions and explain the results by linking the CF model. In addition, an array mapping scheme to transfer weights to one transistor-one RRAM (1T1R) array is experimentally demonstrated. Through NN simulations, we verify that the probabilistic NN shows promising results on nonlinear classification problem avoiding overconfidence compared with deterministic NN. [ABSTRACT FROM AUTHOR]

Neuromorphic computing has gained a considerable research interest due to its potential in realizing highly efficient parallel computations. However, the existing neuromorphic architectures face various drawbacks. In this study, we present an integrate-and-fire (I&F) neuron using a Li-based electrochemical random access memory (Li-ECRAM) to achieve exceptional area efficiency and low-power neuromorphic computing. The proposed Li-ECRAM neuron employs a significantly reduced number of transistors when compared to other novel nonvolatile memory-based I&F neurons due to linear current integration characteristics and a high linear conductance response to the input current. As the integration-type Li-ECRAM is linear, it eliminates the requirement of a nonlinear compensating circuit. Therefore, a Li-ECRAM-based neuron has a simple structure comprising Li-ECRAM, reset transistor, inverter, and pulse generator. Furthermore, we also evaluate the operation speed and energy consumption of the proposed neuron, demonstrating the potential for high-speed and low-power operation. The proposed neuron can be applied in large-scale neuromorphic hardware applications due to the scalability and low energy consumption of Li-ECRAM. [ABSTRACT FROM AUTHOR]

High-pressure hydrogen annealing (HPHA) treatment is an effective hydrogen doping method to improve electrical characteristics and stability of InGaZnO (IGZO) thin film transistors (TFTs). The HPHA effects on IGZO TFTs under various pressure conditions were investigated using analytical techniques. Drive current, field effect mobility, subthreshold swing, and bias stress stability of IGZO TFTs were significantly improved as the HPHA pressure was increased up to 20 atm. To analyze the performance enhancement, secondary ion mass spectroscopy, capacitance–voltage analysis, and x-ray photoelectron spectroscopy analysis techniques were performed. As a result, it was confirmed that doped hydrogen is combined with interface trap sites and oxygen vacancy related bulk defect sites, leading to improved subthreshold swing and bias stress stability. Furthermore, bulk trap passivation also contributes to high carrier density, thereby increasing driving current and field effect mobility. With increasing HPHA pressure condition, these effects of trap passivation and increase in the carrier density are more effective due to the heavily injected hydrogen. [ABSTRACT FROM AUTHOR]