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Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time. [ABSTRACT FROM AUTHOR]

The increasing complexity of modern superconductive circuits, and single flux quantum (SFQ) circuits in particular has made the issue of flux trapping of growing importance. The use of wide superconductive striplines for signal routing has exacerbated this issue. Trapping residual magnetic fields in these striplines degrades performance while reducing margins, damaging the operability of superconductive circuits. In this article, an area efficient topology for striplines is introduced to manage flux trapping in large scale SFQ circuits. This topology is composed of narrow parallel lines in series with small resistors. The proposed topology decreases the length of the striplines by exploiting the mutual inductance between the narrow parallel lines. The topology requires significantly less area while preventing flux trapping within wide superconductive striplines. The narrow parallel line topology also reduces coupling capacitance between striplines. The proposed approach is compatible with automated routing of large scale SFQ integrated circuits. [ABSTRACT FROM AUTHOR]

Inductance in superconductive circuits plays a significant role in rapid single flux quantum (RSFQ) systems. Inductance estimation is a challenging issue. The microwave behavior of these inductances is characterized by the surface inductance of a line. A methodology to accurately estimate the surface inductance of a stripline is the focus of this brief. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is provided. The effects of process parameter variations on the surface inductance are also discussed. An expression to model the effects of the trapezoidal geometry of a stripline is presented. The dependence of the surface inductance on the oxide and metal layer thicknesses is also presented. The objective is to provide an accurate estimate of the surface inductance for use in automated routing of VLSI complexity RSFQ circuits. [ABSTRACT FROM AUTHOR]

The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved. [ABSTRACT FROM AUTHOR]

Superconductive passive transmission lines (PTL) are widely used for signal routing in large-scale rapid single flux quantum (RSFQ) circuits. Due to the imperfect matching of the transmission lines between the driver and receiver, single flux quantum (SFQ) pulses are partially reflected. The round trip propagation time of these reflections can coincide with the following SFQ pulse, resulting in a decrease in bias margins or incorrect circuit behavior. This resonant effect depends upon the length of the PTL and the clock frequency of the signal. A methodology to reduce and manage this effect is the focus of this article. A closed-form expression describing the dependence of the resonance frequency on the length of the PTL is presented. This expression describes a set of forbidden lengths for PTL interconnect segments in RSFQ circuits. The proposed methodology and algorithm insert active PTL-based repeaters into long superconductive interconnect while ensuring the length of the line segment is outside the forbidden region and increasing bias margins. [ABSTRACT FROM AUTHOR]

We have investigated various geometrical design dependencies for rapid single-flux-quantum (RSFQ) circuits in high- $T_{c}$ superconductors (HTS) technology, including the characteristics of the intermediate inductances. Structural- and temporal- dependent combinations of ${C}_n$ – $R_{n}$ (capacitance and normal resistance of the Josephson junctions, JJs) in the HTS technology are also investigated. Relatively favorable combinations of normal resistance and low capacitance of the JJs needed in the HTS technology for RSFQ circuits have been made possible by recent fabrication methods of high-quality YBCO films. Obtaining these devices is made achievable by using the grain boundary structures and high critical current density (JC) of the HTS JJs. Mutual interactions of the intermediate inductances with other parts of the whole circuit are examined and optimized for the best operation situation. Here in particular, the operation of the HTS Josephson-transmission-line (JTL) cells utilizing the grain boundary Josephson junctions, including various structural inductances, is studied based on the reported parameters of the developed devices and thoroughly analyzed by simulation results. [ABSTRACT FROM AUTHOR]

Considering the two main categories of rapid single flux quantum gates with destructive and nondestructive readout process, we have investigated the effects of readout cell topology and involved critical parameters on the proper functionality and stability of the states of the newly developed bidirectional T flip-flops (TFFs). It is observed that instabilities and fluctuations in the state of the gate (memory of TFF) after each transition determine the minimum time intervals between the clock pulses set by the ac bias current, further limiting the ultimate operation frequency of the circuits. The absolute values of the current levels of the junctions at each state, which play an important role in the behavior of the cell, are studied, and their variations over several consequent pulses are stabilized by optimizing the cell parameters. The appropriate values of the circuit and junction parameters are found, resulting in the optimum operation of the circuit for having the best margins possible. We report on the investigated circuit topology and parameter optimizations of the readout circuit of the considered bidirectional TFF. [ABSTRACT FROM PUBLISHER]