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Most of the reduced switch multilevel inverters (MLIs), including switched capacitor MLIs (SC-MLIs), are designed with voltage sources/capacitors have obtained voltage levels with the addition of these sources only. This increases the number of voltage sources (capacitors) without full utilisation of these sources and has higher inverter total standing voltages, which leads the inverter inefficient (high conduction loss) and costly. The motivation of this work is to design a generalised reduced component MLI aiming for addition as well as subtraction of the voltage sources to obtain a voltage level, which results in the reduction of sources, enhance the voltage utilisation and lowering the inverter total standing voltage (TSV). The design parameters of the proposed MLI topology are compared with the recently developed MLIs in terms of the number of switches, capacitors and TSV to prove its superiority. The experimental prototype of the specimen 15-level and 27-level inverters is implemented using DS1103 and the corresponding results are presented. [ABSTRACT FROM AUTHOR]

The maximum power point tracking concept is essential in PV systems to increase the power transfer capability and efficiency. The conventional methods to track maximum power point perform satisfactorily only under uniform solar irradiation, however under partially shaded conditions, PV array offers several local maxima along with one global maximum power transfer point on the P-V curve. This makes optimal tracking more difficult. This paper proposed an improved adaptive MPPT algorithm with varying step size to track the Global Maximum Power Point (GMPP) under different partial shaded conditions. First, the simulation model has been analyzed which is suitable for partially shaded conditions and then the proposed Variable Step-size Adaptive Maximum Power Point Tracking (VSAMPPT) method has been developed to track the global optimal power point for various irradiations. Here changing the duty cycle is not with fixed step size but with variable step size (Dstep), which depends on the square of the difference between the ratio of voltages to current and makes the proposed algorithm faster. The proposed algorithm keeps on adjusting its tracking strategy to find Global Peak Area (GPA) where the global maximum power point can be tracked down very easily. The proposed algorithm has been validated in the laboratory with dSPACE (DS1103) and tested with different case studies. The results demonstrate the effectiveness of the proposed concept over the existing MPPT methods like P&O method, Incremental Conductance (IC), and Adaptive MPPT methods in terms of speed of tracking global maximum power point, accuracy, and flexibility. [ABSTRACT FROM AUTHOR]

Switched-capacitor (SC) multilevel inverters (MLIs) offer various advantages over conventional series MLIs owing to the operation from a single dc source, self-balanced capacitor voltages, and inherent voltage gain. However, these advantages come at the cost of high current stress on the capacitors, associated semiconductors, and the dc source. This inrush current has limited the practical application of SC-MLIs to a fractional kilowatt rating. This article proposes a practical solution by introducing a unity gain nine-level active-neutral-point-clamped SC-MLI with an alleviated capacitor charging current. Switching loss in the SC circuit semiconductors is reduced by using a modified switching sequence that allows the charging current to flow with a minimum interruption till it is turned off at zero-current crossing. The structure also integrates protection against the detrimental effects of voltage transients across the charging inductor. The inverter exhibits a maximum efficiency of 98.03% at 583.91 W output power. Compared with similar SC-MLIs with hard-charging, the proposed inverter significantly reduces the losses and improves efficiency. Experimental results from a 2 kVA laboratory prototype validate the theoretical analysis and show the capacitor voltages stable under varying load impedance and modulation index. [ABSTRACT FROM AUTHOR]

In this paper, the generalized and new cascaded modular multilevel inverter topology is presented that is designed with reduced power electronic components. Each module comprises ten power switches (2 bi-directional and 8 unidirectional) and five DC sources. Lower voltage rating switches are employed for this topology due to its remarkable advantage of generating both positive and negative voltage levels without using any H-bridge at the output. Various DC voltage magnitude or MLI algorithm of the proposed topology can be selected to obtain different voltage levels. The most optimal inverter algorithm is selected and further design a generalized cascaded structure for high voltage applications that requires lesser components and has better performance. The performance of the proposed optimal algorithm is determined and are compared with the various other state-of-art MLI topologies. The specimen 27-level inverter of the proposed configuration is modulated using the sinusoidal-PWM (SPWM) technique and is implemented in the laboratory prototype of the experimental setup using a d-SPACE 1103 controller. The performance parameters of the proposed topology stand better than other existing and compared MLI topologies in terms of the variety of DC sources, number of DC sources, number of voltage levels, and number of driver circuits. Regarding the economic reliability of the proposed inverter, total standing voltage (TSV), cost factor per level (CFL) have also been calculated. The experimental results of the 27-level output voltage at different load verify its performance. [ABSTRACT FROM AUTHOR]

Most of the switched capacitor multi‐level inverters (SC‐MLIs) are designed with a single isolated voltage source and capacitors where voltage levels are obtained by the addition of these sources only. The common problems arise in SC‐MLIs are an unequal number of conducting paths, higher voltage drop across capacitors, sum of total inverter DC link voltages across the highest voltage rated switches and higher total standing voltage (TSV). The motivation of this work is to design a hybrid generalized SC‐MLI with reduced components aiming to maintain a constant voltage across the capacitors, to achieve higher voltage gain with minimum components used, minimum conducting paths, lower TSV, cost‐effective and an efficient inverter. A generalised SC‐MLI structure is also proposed, which can multiply the voltage across the capacitors in a binary asymmetrical manner. The design parameters of the proposed hybrid SC‐MLI topology are compared with the recently developed SC‐MLIs in terms of the number of switches, capacitors, TSV, conducting switches and industrial components cost to prove its superiority and effectiveness of the proposed inverter. The experimental prototype of a specimen 9‐level and 17‐level inverters are implemented using DS1103 and the corresponding results are presented. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) have become more popular due to the high-quality output waveform with higher voltage levels, lower voltage stress across the power switches, and lower harmonic distortion of the output voltage. This paper introduces two new structures of MLI based on a modified T-type inverter and switched-diode cell. Proposed inverter topologies cascaded in series due to its generalized structure. Inherent property to generate the negative voltage levels without using any full H-bridge circuit is a key feature of the proposed topology. The merit of the proposed inverter is the reduction in power electronic components, the assessment has been carried out with some recent MLI topologies, and graphs relating to the performance parameters have also been incorporated as well. Besides, total standing voltage (TSV) and the level to switch ratio (LSR) is calculated for further clarification of the proposed inverter, and the parameters are compared with the newly developed MLI topologies. A multi-carrier pulse width modulation strategy (MC-PWM) is adopted for the generation of the switching pulses. [ABSTRACT FROM AUTHOR]

A novel asymmetrical nine-level inverter topology using only six switches along with its generalized structure are presented in this paper. The proposed reduced switch multilevel inverter topology makes use of a lower total standing voltage for a required output voltage as compared to the existing ones. One of the major advantages of the proposed multilevel inverter over other existing topologies is that, the circuit can be extended to a higher-level inverter, by cascading a few proposed inverter modules and can also be extended to the three-phase structure very easily, thereby making the inverter structure simple. In addition to this, the proposed inverter module does not require any additional H-bridge circuit to obtain the negative voltage levels for AC voltage, resulting in reduced voltage stress on the switches. This paper also incorporates an effective technique to determine the total standing voltage as well as the switching and conduction losses of the inverter. The MATLAB/Simulink based proposed nine-level as well as an 81-level inverters are modeled and the simulation results are presented. An experimental prototype of nine-level inverter using six switches is developed and tested to validate the simulation results. [ABSTRACT FROM AUTHOR]

In this paper a modified space vector pulse-width modulation (SVPWM) technique for a three-phase T-type inverter is pro- posed that utilizes the state redundancies for fault-tolerant ap- plication. The performance of the T-type, 3-level inverter is analyzed with a three-phase induction motor load under the open-circuit fault condition of the inverter. The voltage space vectors of the three-level inverter under the open switch fault (open circuit fault) condition in any one leg of the three-phase inverter is analyzed and modified using the SVPWM adopted to overcome the problems of sudden stall at open switch fault conditions. Modelling and simulation of T-type 3-level inverter using proposed modified space vector pulse width modulation is carried out in the MATLAB/SIMULINK environment. The experimental results are presented here for verification of the simulation results using real-time simulator (dSPACE 1103). [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) emerged as a boon to the industries due to the fact that it fulfils different industrial aspects such as reduced electromagnetic interference, lower maintenance, less installation area and reduced harmonic content. MLI generates a staircase output voltage with suitable combination of power devices and DC voltage sources. In this work, a generalized cascaded MLI is proposed that employs only a half-bridge converter rather than the full H-bridge converter for the polarity-reversal (on which the maximum DC link voltage appears) and thereby also reduces the required number of power switches. Five different types of algorithm in the proposed configuration have been studied and the most optimal algorithm is further elaborated and implemented. A specimen 7-level inverter of the proposed configuration is modeled in MATLAB/Simulink and is further implemented in the laboratory using the controller DS1103. The experimental results for different modulation indices are further amalgamated and verified with the simulation results. Nevertheless, a comparative assessment of different performance-related parameters of the proposed topology along with the generalized expressions is carried out and are also compared with some of the recently published MLI topologies. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLI) with reduced components are becoming popular to achieve higher voltage levels with lower cost and complexities of the circuit. Most of the reduced switch MLIs use a large number of isolated voltage sources that have a large total standing voltage (TSV) and higher losses. Moreover, many reduced component MLIs have been developed to reduce the number of switches only and have not utilized the dc-link voltages properly. Thus, an inverter needs to be designed in which the number of dc sources is also small and utilized fully. In this paper, a novel single-phase, multicell MLI configuration is presented that can generate a maximum number of output voltage levels using a minimum number of switches and dc sources. Two optimal configurations of the proposed MLI are proposed based on the minimum requirements of components with the optimum voltage stress of the highest rated switches. Moreover, the TSV of the proposed optimal MLI also becomes low. A generalized multicell optimum MLI is presented and the number of components, voltage stress of all the switches, and the TSV of the proposed as well as the other inverters also determined by the generalized expressions for comparison purpose. The prototype of a specimen 15-level inverter and the optimal 75-level inverter cell is further developed and implemented using DS 1103 in the laboratory to show the effectiveness of the proposed configuration. The experimental results corresponding to the different modulation indices are presented here for the verification of the simulation results. [ABSTRACT FROM AUTHOR]

Reduction in the overall power devices such as power semi-conductor switches, gate drivers with the associated circuits and DC voltage sources reduces the size, cost, complexity in addition with enhancing the overall performance of the inverter. This paper presents a new and generalized multilevel inverter topology with reduced number of power components. To identify the significance of proposed inverter, the generalized formulae for all the parameters are calculated and a comprehensive comparison of different performance parameters are presented in tabular as well as in graphical form. Multicarrier pulse width modulation strategy is adopted for generating the switching pulses. Simulation of the proposed MLI topology for the 9-level and 17-level inverter have been performed in MATLAB/Simulink and the corresponding experimental results are incorporated for one unit and two units, respectively, experiments are carried out at RL load. Nevertheless, level per switch Ratio (L/S) is introduced and compared with some of the new discussed MLI topologies. Moreover, the switching and the conduction losses of the inverter are also calculated and incorporated in this paper. [ABSTRACT FROM AUTHOR]

A single-phase cascaded generalized doubling circuit-based multi-level inverter configuration is presented that can generate maximum number of output voltage levels by distributing the total asymmetrical input DC link voltage among the cells using minimum number of power switches. A cell consists of n numbers of sub-cells each having two DC voltage sources connected in series along with a half-bridge circuit and a polarity reversal unit. Moreover, an optimum structure of novel proposed MLI is presented and well described in the paper. A laboratory prototype of proposed 15-level MLI is developed and the experimental results are found at par with the simulation results. The experimental results are captured for different modulation indices to show the effectiveness of the proposed MLI that can be used for Photovoltaic (PV) applications. [ABSTRACT FROM AUTHOR]

Multilevel inverter (MLI) generates stepped voltage with appropriate switching combination of power devices, thus restraining the requirement of filter circuit for an efficient power conversion. MLIs are attracting due to some of the major features like economic cost, installation space, bulkiness, complexity along with its enormous applications in industries like cement factory, ceramic industry, aerospace applications etc. In this paper, a single-phase generalised inverter based on five different algorithms is proposed that uses the minimum of overall power components. The presented topology can be used in low and medium voltage applications. To verify the simulation results obtained by MATLAB/Simulink, DS1103 controller is used to generate the corresponding experimental results by developing a prototype model in the laboratory. Nevertheless, a comparative assessment for the different required components of the proposed topology is carried out with some recently developed topologies. Reduction in power switches, driver circuits and DC voltage sources reduces the size, cost, complexity and enhances the overall performance. In addition, level per switch ratio is added in this paper to decide the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This article presents a generalised asymmetrical cascaded multilevel inverter (MLI) for a single‐phase grid‐connected photovoltaic (PV) system and their control strategy. The control strategy, including maximum power tracking along with a suitable interface, is implemented for maximum power transfer from the PV source to the single‐phase low‐power grid. The balancing of DC‐link voltages for an asymmetrical MLI under variable solar parameters as well as grid parameter variation is implemented using the proposed control strategy. The voltage controllers maintain the constant DC‐link voltage ratio, whereas the current controller injects the sinusoidal current into the grid at unity power factor and track the grid voltage under variation of grid voltage using grid tracker. Stability analysis of the proposed grid‐connected asymmetrical inverter system is also incorporated. The whole grid‐tied PV system is simulated in the MATLAB/SIMULINK environment and the exhaustive simulation results of the system under different transient conditions are presented. In addition, a laboratory prototype for a low‐power grid‐tied PV system has been developed and implemented using DS1103. The performance of the system is also tested at varying irradiance conditions and the corresponding experimental results are also presented. [ABSTRACT FROM AUTHOR]

This study presents the performance analysis of a new asymmetrical multi‐level inverter using reduced number of switches for a single‐phase grid‐tied photovoltaic (PV) system. The solar PV panels of unequal power rating are connected in an appropriate manner to obtain the DC link voltages of suitable ratio for an asymmetrical cascaded multi‐level inverter. The PV power, voltages as well as the current injected into the grid have been controlled using the separate maximum power point tracking, voltage controllers and a current controlled technique to achieve the maximum power with sinusoidal current with a unity power factor. The variations of DC link voltages, inverter voltage and injected grid current are simulated and are experimentally verified under the variable irradiation as well as grid voltage fluctuation. The simulation and the corresponding hardware results of the proposed reduced switch asymmetrical seven‐level inverter for a low‐power residential grid‐tied PV system is also presented. [ABSTRACT FROM AUTHOR]

A multilevel inverter (MLI) with staircase waveform having maximum number of voltage levels at any desired voltage (or frequency) of a variable voltage, variable frequency application can play an important role in the modern power conversion system. In most of the control and modulation techniques of MLI, the number of voltage level reduces with the reduction of modulation index that increases the harmonic and total harmonic distortions (THDs). The variable voltage application of MLI using a single DC source of variable magnitude is the elementary concept of the proposed control technique. A cascaded MLI having unequal voltage sources with controlled magnitude can be used to increase the number of voltage levels. The closed-loop voltage control technique and a multi-winding transformer-rectifier based AC-link system is used to obtain the multiple variable voltage DC sources for the cascaded MLI. A nearest level modulation based control technique has been implemented for the MLI to obtain the fixed level voltage waveforms with constant THD and reduced switching losses. The whole control algorithm for a nine-level inverter is simulated and results are experimentally verified on a laboratory prototype of the three-phase induction motor drives. [ABSTRACT FROM AUTHOR]

A novel and generalised three-phase multilevel inverter (MLI) with a minimum number of switches have been proposed. The number of voltage levels can be increased to a significant value by incorporating few switches and the DC voltage sources. In the proposed three-phase MLI, the number of phase-voltage levels can be increased twice as the number of switches increased. The detailed analysis of the proposed MLI, mathematical modelling of the inverter voltage and the switching loss calculation have been done for a seven-level inverter. Modelling and simulations of the proposed generalised three-phase inverter are carried out using MATLAB/SIMULINK. The simulation results of the proposed multilevel configuration corresponding to the different voltage levels as well as at different modulation index are presented. A laboratory prototype of the proposed five-level inverter has been developed and tested for the speed control of an induction motor. The experimental results for the different modulation indexes are presented, that verifies the simulation results. A detailed comparison of the proposed MLI with the other popular multilevel configuration is presented to reflect the merits of the proposed structure for the reduced component count. [ABSTRACT FROM AUTHOR]

This study presents a generalised online switching scheme for a space vector pulse-width modulation (SVPWM)- based multilevel inverter of any voltage level. The proposed SVPWM algorithm implements a generalised three-(similar to five) and seven-segment switching scheme using the three most desired switching states and one suitable redundant state for each triangle. In addition, a novel three-segment and seven-segment switching scheme has been proposed, which eliminates extra switching commutations and hence minimises the switching frequency of the devices while reducing harmonics. The proposed modulation algorithm using the generalised expressions is implemented online. The performance of the proposed novel algorithm for N-level inverter is tested experimentally on a five-level cascaded inverter at various fundamental frequencies and the experimental results are verified with the simulation results. [ABSTRACT FROM AUTHOR]

This study presents a simple and a generalised space vector pulse-width modulation scheme for a neutral point clamped multi-level inverter as well as cascaded inverter of any level. This modulation algorithm implements the online generation of desired switching states and their sequences through generalised expressions without any predetermined stored data in a memory look-up table. The proposed algorithm also incorporates the concept of reference vector and on-time modification combined during the over-modulation region for any level of inverter. Performance of the proposed modulation algorithm is tested experimentally through a digital signal processor-based controller for a five-level cascaded inverter with very low execution time that does not depend much on the level of inverter. The simulation waveform and the harmonic analysis of the voltage at different modulation index are presented and these are verified with the experimental results. [ABSTRACT FROM AUTHOR]

Summary: The proposed work shows a novel multilevel inverter (MLI) configuration to generate a large number of voltage levels with lesser number of power switches. The proposed generalized inverter comprises basic cells cascaded to each other. Each cell of the proposed inverter can generate three‐level AC voltage using the power switches of the same rating. Both single‐phase and three‐phase MLI configurations are possible for the proposed structure. To validate the performance of the proposed MLI configuration, a nine‐level inverter using six power switches and a 27‐level inverter using nine power switches are designed and simulated in the MATLAB/Simulink environment. An experimental prototype is developed in the laboratory, and the experimental results are presented to verify the simulated results. Further, to validate the effectiveness of the proposed multilevel inverter, a comparison of the proposed MLI with recently proposed multilevel inverter has been incorporated in a detailed manner. [ABSTRACT FROM AUTHOR]

Summary: In this research work, a generalized structure of multilevel topology is proposed that can be extended by cascading the modules. Proposed modular topology is modified T‐type structure that requires comparative reduced number of power components than other existing structures of multilevel inverter. Each module encompasses of three DC sources and 10 power switches. Both positive and negative voltage levels can be generated without the use of H‐bridge inverter; thus, lower voltage rating power switches are employed for proposed modular topology. To generate the output voltage levels, the nearest level control is implemented on the experimental setup using dSPACE 1103 controller. To verify the performance of the proposed inverter, experimental validation of various topologies based on different algorithms is performed to generate 15‐level, 17‐level, 27‐level, and 31‐level at different load conditions. Moreover, different state‐of‐art topologies are compared with proposed topology in terms of the required number of voltage levels, DC sources, power switches, driver circuits, and total standing voltage. [ABSTRACT FROM AUTHOR]