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This study presents the design of a large DC series‐parallel windfarm that considers the key operational challenges in determining the optimal generator equipment rating and DC transmission voltage control. With this topology, offshore platform is not needed, but wind speed dispersion over windfarms and generator outage possibilities demand generator DC output voltages beyond their ratings. An optimization algorithm is developed along with a complete cost model, which includes operational and capital costs with all topology options, in order to inform design decisions. The results are evaluated on a 100‐generator, 25 × 4, 1 GW, 525 kV test wind farm and performance is verified using detailed PSCAD/EMTDC time‐domain simulation. The key finding is that a positive net present value (NPV) is achieved, avoiding power curtailment even under 3% generator outage, when an overvoltage coefficient of 1.145 pu is utilised on all wind generators, assuming use of a suitable DC transmission voltage control. Further, a wide‐ranging parameter sensitivity analysis is performed, and tower arrangement for insulation requirements is proposed. [ABSTRACT FROM AUTHOR]

The article analyses design options for a practical 2-10 kV, 1-2 kA LC DC Circuit Breaker module. The impact of multiple series break points with the ultra-fast disconnector is explored in depth using analytical model and 5 kV, 4-break hardware prototype. The experimental testing demonstrates that the arc voltage increases proportionally with each breaking point, and this increases current that can be internally commutated. Further analysis of the impact of delays between break points is presented. Modeling and testing with 4 different capacitors of 1-10 kV concludes that larger capacitances increase commutating current, but relationship is complex and non-linear. Parallel connection of breaking points is also analysed. Successful breaking of DC fault current is demonstrated on hardware for multiple cases including 930 A with 800 $\mu$ F, 6.5 kV, capacitor using a 4-break disconnector. The tested DC CB is of mechanical type, which inserts a capacitor in series in a very short time of around 290 $\mu$ s, and full contact separation is achieved 1.5 ms after the trip signal. It is recommended that the module design should primarily consider maximizing the number of break points in series. [ABSTRACT FROM AUTHOR]

This article describes design, operation and experimental testing of a mechanical DC CB (Circuit Breaker) with parallel capacitors. The topology resembles hybrid DC CB but there are possible advantages in the costs since the main semiconductor valve is replaced with capacitors, and in performance since this breaker inserts counter voltage earlier. A detailed PSCAD model is employed to support DC CB design and to analyse operating principles. A 5 kV, 2 kA hardware demonstrator with 1.5 ms disconnector opening time is developed in the university laboratory. The test results demonstrate successful breaking of DC currents, with the measured time for insertion of capacitor voltage of around 290 μs. Further experimental analysis evaluates stresses on the key components, optimal timing for opening of LCS (Load Commutation Switch) and the margins for successful current interruption. [ABSTRACT FROM AUTHOR]

In this paper, an analytical framework for minimizing losses and harmonics is presented for the cascaded-type-based multilevel static synchronous compensator (STATCOM) with 'square-wave control.' The focus lays on low losses, low-voltage total harmonic distortion (THD), and low dc voltage ripple. All of the system parameters are studied, including buffer reactance, dc capacitance, transformer ratio, and transformer leakage inductance. The equivalent capacitance concept is used to represent the complex structure of the multilevel converter. It enables studies of the internal STATCOM resonances which have a significant influence on triplen harmonics and losses. The interactions between system parameter are investigated and analytical formulae for optimal parameters are derived. Detailed PSCAD digital simulations are used to confirm the analytical formulae. The summarized design steps are offered that are recommended to obtain optimum STATCOM system parameters. Index Terms--Harmonic distortion, multilevel converter, resonances, static synchronous compensator (STATCOM), static VAR compensators.

This paper develops a frequency-dependent analytical representation for a multilevel cascaded converter, with fundamental frequency switching. The gain and phase angle are studied with the firing angle as a parameter, where the converter is subjected to oscillatory excitation at a range of frequencies. This paper presents analytical formulae for a single cell and for a generic cascade multilevel converter where the number of cells is a parameter. Also, the formula for fundamental frequency studies is separately developed. The equivalent capacitance concept is introduced and its convergence to a constant value for high frequencies is demonstrated. The analytical formulae are tested against detailed digital simulation and good matching is reported. The formulae developed in this study will be of particular importance in studying interactions between a multilevel STATCOM and the host ac grid (similar to harmonic resonance) and in studying converter transient responses. Index Terms--Frequency response, multilevel converter, static VAR compensators.

This paper presents a novel converter configuration, based solely on conventional thyristors and aimed for the use with high voltage dc (HVDC) transmission. The converter utilizes resonant turn off and forced commutation with auxiliary thyristors to aid commutation in the converter switches. The PSCAD/EMTDC simulation confirms that the HVDC inverter is capable of operating with a wide range of firing angles, including operation with reactive power export. Further simulation proves that the system is immune to commutation failure even in the case of most severe close single-phase faults. The harmonic generation is comparable to the conventional converter and also the thyristor voltage stress is not significantly increased. The auxiliary thyristors do increase costs, but this is offset by the elimination of reactive power support and the improvements in performance. Index Terms--Commutated circuits, HVDC converters, HVDC transmission, reactive power.

This paper studies the use of a voltage-source converter (VSC) with dc capacitors as an energy storage medium for the compensation of pulsating active and reactive power of the European Organization for Nuclear Research's (CERN's) proton synchrotron (PS) particle accelerator. The PS accelerator load demands periodic, active, and reactive power pulses of about 2-s duration and a magnitude of up to 45 MW and 65 Mvar. The proposed compensator is able to control both reactive and active power exchange with the network in order to eliminate network disturbances. The controllability study reveals that the best control strategy is to use a q-axis converter input for active power and a d-axis input for reactive power regulation. An analytical system model is created to study the system dynamics and to aid the controller design. The eigenvalue study with the MATLAB model reveals that with large energy storage units and small converter losses, there is only a small interaction between the control channels. The final testing is done with a detailed nonlinear model in PSCAD/EMTDC. The simulation results show that it is possible to fully compensate the active power exchange with the network during typical accelerator cycles and, at the same time, to achieve excellent ac voltage control. Index Terms--Accelerator power supply, eigenvalues, energy storage, proton accelerators, pulsewidth-modulated power converters, root loci, state-space methods.

This paper presents an analytical, linear, state-space model of a thyristor-controlled series capacitor (TCSC). First, a simplified fundamental frequency model of TCSC is proposed and the model results are verified. Using frequency response of the nonlinear TCSC segment, a simplified nonlinear state-space model is derived, where the frequency of the dominant TCSC complex poles shows linear dependence on the firing angle. The nonlinear element is linearised and linked with the ac network model and the TCSC controller model that also includes a phase-locked-loop (PLL) model. The model is implemented in MATLAB and verified against PSCAD/EMTDC in the time and frequency domains for a range of operating conditions. The model is sufficiently accurate for most control design applications and practical stability issues in the subsynchronous range. Index Terms--Modeling, power system dynamic stability, state-space methods, thyristor converters.

This paper presents a linear state-space model of a static VAR compensator. The model consists of three individual subsystem models: an ac system, a SVC model, and a controller model, linked together through d--q transformation. The issue of nonlinear susceptance-voltage term and coupling with a static frame of reference is resolved using an artificial rotating susceptance and linearizing its dependence on firing angle. The model is implemented in MATLAB and verified against PSCAD/EMTDC in the time and frequency domains. The verification demonstrates very good system gain accuracy in a wide frequency range f < 150 Hz, whereas the phase angle shows somewhat inferior matching above 25 Hz. It is concluded that the model is sufficiently accurate for many control design applications and practical stability issues. The model's use is demonstrated by analyzing the dynamic influence of the PLL gains, where the eigenvalue movement shows that reductions in gains deteriorate system stability. Index Terms--Modeling, power system dynamic stability, state space methods, static VAR compensators, thyristor converters.

This research addresses the special requirements of phase locked loops (PLLs) for a typical application with FACTS elements. A new PLL system that uses adaptation algorithms is developed with the aim of improving speed of responses, robustness to AC voltage depressions, and harmonic rejection. The adaptive PLL consists of the three control units that individually control frequency, phase angle, and voltage magnitude. The voltage controller output is used to compensate for reduced gain caused by the ac voltage magnitude depressions. The output phase angle and its derivative, the frequency signal, are controlled in two independent control systems in order to enable elimination of frequency and phase error without compromising transient responses. The simulation results are compared with a PLL available with the PSB MATLAB block-set and noticeable improvements are demonstrated. In particular, settling time and overshooting are significantly lower with conditions of reduced ac voltage magnitude. Index Terms--Frequency locked loops, modeling, phase-locked loops, power system control, thyristor circuits, tracking.

HVDC grid protection with adequate speed and reliability is required to minimise the impact of DC faults. In particular, fast breaker failure backup protection algorithms are needed to meet the expected reliability requirements of HVDC grids. In this paper, existing breaker failure backup protection algorithms are shown inadequate to detect partial failures like a single module failure of breakers with a modular structure. This paper proposes a backup protection algorithm which rapidly detects a DC breaker failure based on estimating the counter-voltage created by the energy absorption branch during an interruption. The performance of the proposed algorithm is evaluated using a four-terminal test network with both hybrid and mechanical DC breaker technologies. The simulation results show that the proposed algorithm is able to quickly detect both complete and partial failures of the two breaker technologies even considering measurement errors, noise and ageing of the energy absorption components. [ABSTRACT FROM AUTHOR]

This paper describes a method of fast commutation of DC current into a capacitor. Theoretical study is provided, which enables evaluation of commutating DC current for the given contact velocity, capacitance, and dielectric strength. It is concluded that a non-zero contact velocity at separation is required, and a corresponding switch design is proposed. Experimental results on a laboratory setup illustrate successful DC current commutation up to 400 A, with voltages rising to 1.3 kV. Further experiments demonstrate that parasitic parameters reduce the magnitude of the current that can be commutated. A detailed non-linear PSCAD model and a linear model for the parasitic circuit are presented to enable prediction of the success of commutation. The model accuracy is confirmed with experimental tests. The DC current commutation in the proposed method occurs 5–10 μs after the contact separation, which is much faster than with other methods employing moving contacts. A further benefit of the extremely short arcing is the elimination of thermal issues on contacts, and possible simplified design of the mechanical switch. [ABSTRACT FROM AUTHOR]

This paper examines two new bidirectional hybrid dc circuit breaker (CB) topologies for application in meshed dc grids. The goal is to retain performance of hybrid dc CB with bidirectional current interruption while reducing semiconductor count, dc CB size, and weight. The fault current is routed to the unidirectional internal valve using multiple additional ultrafast disconnectors. Operation of both topologies is studied using a 320-kV, 16-kA simulation model, as well as demonstrated on a 900-V, 500-A lab prototype. The control systems are presented and discussed in detail. The low-voltage hardware prototypes verify performance of several new technical and operating solutions in laboratory conditions. A comparison is made with the existing dc CB topologies and performance and reliability compromises of each topology are assessed. The conclusion is that it might be possible to halve the dc CB semiconductor count while retaining same 2 ms opening speed and bidirectional operation. [ABSTRACT FROM AUTHOR]

Since the late 19th century, ac power transmiss ion systems have been widely used for interconnecting multiple power-producing plants with load centers. Highly meshed ac transmission grids with high redundancy and operating flexibility now operate worldwide. These complex ac systems have proven reliable in securely providing high levels of power, while also accommodating multiple voltage levels to reduce loss. [ABSTRACT FROM AUTHOR]

Peak fault current and energy dissipation in high-voltage direct current (HVdc) circuit breakers (CBs) are very important parameters that impact dc grid protection development. This paper analyzes a hybrid DCCB (HCB) control that reduces peak current and energy dissipation by regulating the voltage across contacts of the ultrafast disconnector (UFD). This is achieved by manipulating the number of inserted surge arresters while contacts of the UFD are moving apart. The controller is seamlessly integrated with the current controller of HCBs. An analytical model for current and energy calculation is presented, verified, and employed for parametric studies. A PSCAD simulation with 320-kV, 16-kA test circuit confirms that the proposed voltage control reduces the peak current and energy dissipation by around 20%–30%. A 900-V, 500-A HCB laboratory hardware is described and the experimental results are shown to corroborate simulation conclusions. [ABSTRACT FROM PUBLISHER]

This paper studies protection and control methods for a large dc grid based solely on full-bridge modular multilevel converters (MMCs). An initial theoretical study concludes that dc circuit breakers (CB) energy dissipation will depend on inductance and square of fault current, but not on protection operating time. Using differential protection is proposed because of robust selectivity and since it operates well with small series inductors. The analysis of dc CB dissipated energy leads to new protection logic design that delays tripping signals until local current reduces to low values. Low-speed dc CB with very small inductors are adequate. The design of controllers for MMC converters should be coordinated with dc grid protection and the study derives values for current controller references. The fault recovery time is found to depend on current reference settings at MMC terminals, and optimal values are derived. The conclusions are confirmed using Electromagnetic Transients Program (EMTP) simulation on a 400-kV, 4-MMC dc grid considering two topologies: with five overhead lines and with five dc cables. [ABSTRACT FROM PUBLISHER]

The inductor-capacitor-inductor (LCL) dc/dc converter has been extensively studied for high power and stepping ratio because of elimination of internal transformer, lower footprint/weight, higher efficiency, and most importantly providing dc fault isolation from both dc sides. This paper presents a two-channel, two-layer controller including two inner current loops, which is symmetrical for each bridge of LCL dc/dc. The real-time implementation of the control scheme and its performance under normal conditions and during transient dc faults at both sides are studied on a 30 kW 200 V/900 V 1.7 kHz prototype. The prototype development is presented in some depth. The experimental results show that the converter with closed-loop control operates well at full power and under fast power reversal. Further dc fault testing concludes that there is no need for blocking since the internal voltage and current variables are within the rated values. Detailed study of converter losses is performed and results show that full power efficiency is around 93.4%. [ABSTRACT FROM AUTHOR]

This paper presents a systematic study on designing a hybrid direct current (dc) circuit breaker (CB) based on fast thyristors. As an illustration, the dc CB main parameters are calculated for a 120 kV, 1.5 kA test breaker with an interrupting current of 10 kA. The studies indicate that the opening time of 2.3 ms can be achieved only if fast thyristors are employed. It is further illustrated that there is a design tradeoff between minimum interrupting current capability and discharge time for the internal capacitors (reclosing speed). The dc CB control system for opening and closing is presented based on different levels of protection and the self-protection. The dc CB is modeled in PSCAD and simulation results are used to evaluate the breaker performance under different operating conditions. It is concluded that the model represents well the dc CB and can be employed for dc grid protection studies. It is further shown that the opening time becomes longer as interrupting current reduces, and it is very long in the case of load current interruption. [ABSTRACT FROM PUBLISHER]

This paper presents the two-channel controller with inner current loops for dual bridge, DC/DC converter, based on modular multilevel converter (MMC) technology. The DC/DC control strategy is based on two inner fast current control loops in dq rotating frame at each of the two MMC bridges. These current controls facilitate operation through dc faults at either dc bus. The active power control is shared by two MMCs, at the slower outer control level. The second outer control loop minimizes losses, which is achieved by feedback control of magnitude of both modulation indices at maximal value of 0.95 at all loading levels. The controller is symmetrical, provides bidirectional power flow and responds equally to faults on either dc bus. Under dc fault conditions, one MMC actively controls the inner ac current, while temporary blocking of MMC on faulted side is required to prevent cell capacitor discharge. The validity of the proposed control is verified on PSCAD using a 600 MW, 500-kV/640-kV test dc/dc model. The controller can be used for control/stability studies with large dc grids that contain dc/dc converters. [ABSTRACT FROM PUBLISHER]

As the future dc grids will involve numerous converter systems, the accuracy and speed of their modelling becomes of high importance. The modelling in a rotating dq frame is able to transform the quantities from ac variables to dc variables resulting in significantly improved simulation speed. dq analytical modelling is normally used only for dynamic studies with voltage source converter (VSC), while large‐disturbance dc faults are commonly studied in static abc frame. A new dq frame modelling method for VSC, including modular multilevel converter topology, for dc fault study is proposed. A unified modelling of the VSC for both dynamic and dc fault study is therefore developed. The model is separately presented for other fault‐tolerant VSC, like LCL (inductor–capacitor–inductor)‐VSC. Simulation results verified that the proposed model is accurate when compared with detailed switching model on PSCAD/EMTDC. The proposed unified VSC model is able to replace the detailed switching model for both dc fault (only pole‐to‐pole dc fault is studied) and dynamic studies. The modelling approach opens the possibility for modelling large dc grids in dq frame for wide range of operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents a subsea DC collection grid with renewable power parks which inherently has robust DC fault protection and flexible expansion capability. By virtue of the applied DC/DC converter and the proposed DJ-Index Clamping control, different sections of the subsea grid are functionally interconnected and in the meantime decoupled in the event of DC faults. The faults are selectively isolated without the need for fast DC circuit breakers and system recovery from the faulty DC intertie branch is achieved by a coordinated operation strategy on DC/DC converters and DC disconnectors (or standard AC circuit breakers). A 200-MW test system is presented which consists of two 100-MW renewable energy sources (tidal stream and wind) and DC collection/transmission grids. The simulation results confirm the N-1 security of the presented topology and good control performance over a range of DC faults. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]