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Short- and long-term neuroplasticity behaviors are key mechanisms for various activities. In this paper, we propose a synaptic transistor with a floating-gate (FG) node and an amorphous InGaZnO (IGZO) channel layer. The proposed device emulates the neuroplasticity functions of both short-term memory (STM) and long-term memory (LTM) through the control of the amplitude and the number of input pulses. The STM operated by ion movement in the gate dielectrics occurs when the input amplitude is relatively small (< 9 V). The LTM operated through the storage of electrons in the FG occurs when the input amplitude is relatively large (>10 V). In addition, as the number of input pulses increases, information is stored for a longer time. Our FG IGZO synaptic transistor could be a promising device solution for brain-inspired computing systems.

Abstract Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (V T), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µFE) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current–voltage (I–V), V T roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (V O) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as V T, SCE, SS, and µFE, of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of V O and O in two-step oxygen anneal process.

Hardware-oriented neuromorphic computing is gaining great deal of interest for highly parallel data processing and superb energy efficiency, as the candidate for replacement of conventional von Neumann computing. In this work, a novel synaptic transistor constructing the neuromorphic system is proposed, fabricated, and characterized. Amorphous indium-gallium-zinc-oxide ( $\alpha $ -IGZO) and Al2O3 are introduced as the channel and gate dielectric materials, respectively. Along with the high functionality and low-temperature processing viability, geometric peculiarity featuring extended gate structure improves the performances of the proposed transistor as synaptic component in the neuromorphic system. The insight into the substantial effect of optimal device structure design on energy efficiency is highlighted.

In this study, we demonstrate both of digital and analog memory operations in InGaZnO (IGZO) memristor devices by controlling the electrode materials for neuromorphic application. The switching properties of the devices are determined by the initial energy barrier characteristics between the metal electrodes and the IGZO switching layer. Digital switching characteristics are obtained after the forming process when Schottky junction occurs at both of top and bottom electrodes. On the other hands, analog resistive switching is achieved when Schottky and Ohmic junctions exist at each side because the applied voltage modulates the Schottky barrier height through the Ohmic contact. In addition, the weight-update properties of the devices are verified depending on identical and incremental pulse schemes. The incremental pulse trains improve the linearity and variation of weight modulation, leading to the stable learning characteristics of neuromorphic system in terms of pattern recognition with MNIST hand-written digit images.

In this work, the correlation between SiO2 deposition thickness and hydrogen content is discussed and the effect of the SiO2 layer on the properties of synaptic InGaZnO (IGZO) TFTs is analyzed. Three types of IGZO synaptic thin-film transistors (TFTs) were fabricated with different gate insulators, and the effect of SiO2 as a gate insulator was investigated. XPS analysis confirmed that the hydrogen content in the Al2O3 and SiO2 layers increased during SiO2 deposition step for all depth regions. Hydrogen injected by the SiO2 layer deposition step was confirmed to improve the memory window through more threshold voltage shift under positive bias stress (PBS) and negative bias stress (NBS) conditions. In addition, the retention characteristics were improved due to the low hydrogen movement velocity in the SiO2 layer. These results contribute to the optimization of the amount of hydrogen, and the proposed device has potential as a synaptic device capable of neuromorphic computing.

Solution-processed carbon nanotubes (CNTs) have recently attracted significant attention as p-type thin-film transistor (TFT) channels due to their high carrier mobility, high uniformity, and low process temperature. However, implementing sophisticated macroelectronics with a combination of single CNT-TFTs has been challenging because it is difficult to fabricate n-type CNT-TFTs. Therefore, in combination with indium-gallium-zinc-oxide (IGZO), which has excellent electrical performance and has been commercialized as an n-type oxide TFT, we demonstrated various hybrid complementary metal-oxide semiconductor integrated circuits, such as inverters and nor and nand gates. This hybrid integration approach allows us to combine the strength of p-type CNT- and n-type IGZO-TFTs, thus offering a significant improvement for macroelectronic applications.

Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

We propose a systematic calculation method for negative bias illumination stress (NBIS)-induced instabilities in amorphous InGaZnO thin-film transistors (TFTs). The proposed method is based on activation energy window (AEW) in subgap energy range, and it can reproduce the NBIS time evolution of I-V characteristics without long-term stress test. Furthermore, it quantitatively explains the effect of oxygen content on the NBIS instability. The AEW, which is employed for emulating the oxygen vacancy ionization, peroxide formation, and hole trapping, has the order of magnitude of 1016-1017 cm-3 for the bias stress of -20 V and the commercial LED backlight of 300 cd/m². The proposed method is expected to play such an important role in the instability awareness of amorphous oxide TFTs. [ABSTRACT FROM AUTHOR]

The effect of direct current sputtering power of indium-gallium-zinc-oxide (IGZO) on the performance and stability of the corresponding thin-film transistor devices was studied. The field effect mobility increases as the IGZO sputter power increases, at the expense of device reliability under negative bias illumination stress (NBIS). Device simulation based on the extracted sub-gap density of states indicates that the field effect mobility is improved as a result of the number of acceptor-like states decreasing. The degradation by NBIS is suggested to be induced by the formation of peroxides in IGZO rather than charge trapping. [ABSTRACT FROM AUTHOR]

Artificial synaptic potentiation and depression characteristics were demonstrated with Pt/CeO2/Pt devices exhibiting polarity-dependent analog memristive switching. The strong and sequential resistance change with its maximum to minimum ratio >105, imperatively essential for stable operation, as repeating voltage application, emulated the potentiation and depression motion of a synapse with variable synaptic weight. The synaptic weight change could be controlled by the amplitude, width, and number of repeated voltage pulses. The voltage polarity-dependent and asymmetric current–voltage characteristics and consequential resistance change are thought to be due to local inhomogeneity of electrical and physical states of CeO2 such as charging at interface states, valence changes of Ce cations, and so on. These results revealed that the CeO2 layer could be a promising material for analog memristive switching elements with strong resistance change, as an artificial synapse in neuromorphic systems. [ABSTRACT FROM AUTHOR]