260 results on '"Kaczer, Ben"'
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2. Investigating the correlation between interface and dielectric trap densities in aged p-MOSFETs using current-voltage, charge pumping, and 1/f noise characterization techniques
3. Comphy v3.0—A compact-physics framework for modeling charge trapping related reliability phenomena in MOS devices
4. A multi-energy level agnostic approach for defect generation during TDDB stress
5. Evidence of contact-induced variability in industrially-fabricated highly-scaled MoS2 FETs.
6. An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage.
7. A multi-energy level agnostic simulation approach to defect generation
8. Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability
9. Separation of electron and hole trapping components of PBTI in SiON nMOS transistors
10. Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range.
11. Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
12. Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes
13. Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs.
14. Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing.
15. Device‐to‐Materials Pathway for Electron Traps Detection in Amorphous GeSe‐Based Selectors.
16. Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model
17. Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?
18. Toward reliability-aware physics-based FET compact models
19. Impact of Externally Induced Local Mechanical Stress on Electrical Performance of Decananometer MOSFETs.
20. A consistent model for oxide trap profiling with the Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique
21. Single- Versus Multi-Step Trap Assisted Tunneling Currents—Part II: The Role of Polarons.
22. On the Modeling of Polycrystalline Ferroelectric Thin Films: Landau-Based Models Versus Monte Carlo-Based Models Versus Experiment.
23. Dose enhancement due to interconnects in deep-submicron mosfets exposed to X-rays
24. A new TDDB reliability prediction methodology accounting for multiple SBD and wear out
25. An analysis of the NBTI-induced threshold voltage shift evaluated by different techniques
26. Evidence that two tightly coupled mechanisms are responsible for negative bias temperature instability in oxynitride MOSFETs
27. Deep Understanding of Electron Beam Effects on 2D Layered Semiconducting Devices Under Bias Applications.
28. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.
29. Reliability of strained-Si devices with post-oxide-deposition strain introduction
30. Theory of breakdown position determination by voltage- and current-ratio methods
31. Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach
32. Impact of heavy-ion strikes on minimum-size MOSFETs with ultra-thin gate oxide
33. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part I: Theory.
34. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part II: Experimental.
35. Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability
36. Consistent model for short-channel nMOSFET after hard gate oxide breakdown
37. Charge trapping in MOSFETs with HfSiON dielectrics during electrical stressing
38. Progressive breakdown in ultrathin SiON dielectrics and its effect on transistor performance
39. Hot-Electron-Induced Punch-Through (HEIP) Effect in p-MOSFET Enhanced by Mechanical Stress.
40. Cyclic Thermal Effects on Devices of Two‐Dimensional Layered Semiconducting Materials.
41. Trigger-when-charged: a technique for directly measuring RTN and BTI-induced threshold voltage fluctuation under use-Vdd
42. Full (V-g, V-d) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs
43. On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in Iota Iota Iota V/High-k MOS Stack
44. Weibull slope and voltage acceleration of ultra-thin (1.1–1.45 nm EOT) oxynitrides
45. Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET.
46. Modeling and Understanding the Compact Performance of h‐BN Dual‐Gated ReS2 Transistor.
47. Modeling of Repeated FET Hot-Carrier Stress and Anneal Cycles Using Si–H Bond Dissociation/Passivation Energy Distributions.
48. Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration.
49. Investigation of the Impact of Externally Applied Out-of-Plane Stress on Ferroelectric FET.
50. Degradation and breakdown of plasma oxidized magnetic tunnel junctions: single trap creation in [Al.sub.2][O.sub.3] tunnel barriers
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