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1. Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model

Author

Kar, Bapi, Sur-Kolay, Susmita, and Mandal, Chittaranjan

Subjects
FOS: Computer and information sciences, Computer Science - Other Computer Science, Other Computer Science (cs.OH), Hardware_INTEGRATEDCIRCUITS
Abstract

Multiple design iterations are inevitable in nanometer Integrated Circuit (IC) design flow until desired printability and performance metrics are achieved. This starts with placement optimization aimed at improving routability, wirelength, congestion and timing in the design. Contrarily, no such practice exists on a floorplanned layout, during the early stage of the design flow. Recently, STAIRoute \cite{karb2} aimed to address that by identifying the shortest routing path of a net through a set of routing regions in the floorplan in multiple metal layers. Since the blocks in hierarchical ASIC/SoC designs do not use all the permissible routing layers for the internal routing corresponding to standard cell connectivity, the proposed STAIRoute framework is not an effective for early global routability assessment. This leads to improper utilization of routing area, specifically in higher routing layers with fewer routing blockages, as the lack of placement of standard cells does not facilitates any routing of their interconnections. This paper presents a generalized model for early global routability assessment, HGR, by utilizing the free regions over the blocks beyond certain metal layers. The proposed (hybrid) routing model comprises of (a) the junction graph model in STAIRoute routing through the block boundary regions in lower routing layers, and (ii) the grid graph model for routing in higher layers over the free regions of the blocks. Experiment with the latest floorplanning benchmarks exhibit an average reduction of $4\%$, $54\%$ and $70\%$ in netlength, via count, and congestion respectively when HGR is used over STAIRoute. Further, we conducted another experiment on an industrial design flow targeted for $45nm$ process, and the results are encouraging with $~3$X runtime boost when early global routing is used in conjunction with the existing physical design flow., A draft of 24 pages aimed at ACM-TODAES Journal, with 10 figures and 5 tables

Published
2018

2. ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing.

Author

Kar, Bapi, Gopalakrishnan, Pradeep Kumar, Bose, Sumon Kumar, Roy, Mohendra, and Basu, Arindam

Subjects
CMOS integrated circuits, INTEGRATING circuits, BIOLOGICAL neural networks, ONLINE algorithms
Abstract

In this article, we present a low-power (LP) anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves LP operation through a combination of: 1) careful choice of algorithm for online learning and 2) approximate computing techniques to lower average energy. In particular, online pseudoinverse update method (OPIUM) is used to train a randomized neural network for quick and resource-efficient learning. An additional 42% energy saving can be achieved when a lighter version of OPIUM method is used for training with the same number of data samples lead to no significant compromise on the quality of inference. Instead of a single classifier with large number of neurons, an ensemble of $K$ base learner (BL) approach is chosen to reduce learning memory by a factor of $K$. This also enables approximate computing by dynamically varying the neural network size based on anomaly detection. Fabricated in 65-nm CMOS, the ADIC has $K=7$ BLs with 32 neurons in each BL and dissipates 11.87 and 3.35 pJ/OP during learning and inference, respectively, at $V_{\text {dd}}=0.75\,\,\text {V}$ when all seven BLs are enabled. Furthermore, evaluated on the NASA bearing data set, approximately 80% of the chip can be shut down for 99% of the lifetime leading to an energy efficiency of 0.48 pJ/OP, an $18.5 \times $ reduction over full-precision computing running at $V_{\text {dd}}=1.2 \,\, \text {V}$ throughout the lifetime. [ABSTRACT FROM AUTHOR]

Published
2020
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3. Design for Manufacturability aware Early Global Routing

Author

Kar, Bapi

Subjects
Global Routing, Unconstrained Via Minimization, Congestion, Design for Manufacturability, Physical Design Flow, Chemical Mechanical Polishing, Routing Region Definition, Loorplanning, Electronic Design Automation, Pin Access, Monotone Staircase Regions
Published
2017

4. ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS.

Author

Bose, Sumon Kumar, Kar, Bapi, Roy, Mohendra, Gopalakrishnan, Pradeep Kumar, Zhang, Lei, Patil, Aakash, and Basu, Arindam

Subjects
*MICROPROCESSORS, *VOLTAGE-frequency converters, *PATTERN recognition systems, *DATA mining, *EPILEPSY
Abstract

To overcome the energy and bandwidth limitations of traditional IoT systems, “edge computing” or information extraction at the sensor node has become popular. However, now it is important to create very low energy information extraction or pattern recognition systems. In this paper, we present an approximate computing method to reduce the computation energy of a specific type of IoT system used for anomaly detection (e.g. in predictive maintenance, epileptic seizure detection, etc). Termed as Anomaly Detection Based Power Savings (ADEPOS), our proposed method uses low precision computing and low complexity neural networks at the beginning when it is easy to distinguish healthy data. However, on the detection of anomalies, the complexity of the network and computing precision are adaptively increased for accurate predictions. We show that ensemble approaches are well suited for adaptively changing network size. To validate our proposed scheme, a chip has been fabricated in UMC 65nm process that includes an MSP430 microprocessor along with an on-chip switching mode DC-DC converter for dynamic voltage and frequency scaling. Using NASA bearing dataset for machine health monitoring, we show that using ADEPOS we can achieve 8.95X saving of energy along the lifetime without losing any detection accuracy. The energy savings are obtained by reducing the execution time of the neural network on the microprocessor. [ABSTRACT FROM AUTHOR]

Published
2020
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