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The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin $\ge 6~\mu \text{A}/\mu \text{m}$ , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~104 along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented. [ABSTRACT FROM AUTHOR]

The potential of source/drain extension (SDE) region engineering in FinFETs for ultra-low voltage (ULV) analog applications is evaluated. Findings reveal the usefulness of the SDE region design in improving intrinsic dc gain and cutoff frequency.

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1=SM×RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2=SM×CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM. [ABSTRACT FROM AUTHOR]

This paper proposes an accurate model to investigate the small-signal microwave parameters of fully strained (FS) and partially relaxed (PR) [Al.sub.m][Ga.sub.1-m]N/GaN high electron-mobility transistors (HEMTs). It is observed that elastic strain relaxation of the [Al.sub.m][Ga.sub.1-m]N layer imposes an upper limit on the maximum two-dimensional electron-gas sheet charge density and is, thus, extremely critical in determining the microwave performance of high Al-content [Al.sub.m][Ga.sub.1-m]N/GaN HEMTs. The model incorporates the effects of strain relaxation of the barrier layer, field-dependent mobility, parasitic source/drain resistance, and velocity saturation to evaluate drain current, transconductance, drain conductance, cutoff frequency, and transit time of FS and PR [Al.sub.m][Ga.sub.1-m]N/GaN HEMTs with different A1 mole fractions. The proposed model predicts a high drain current of 5.94 A/mm for a PR 0.3-/[micro]m [Al.sub.0.4][Ga.sub.0.6]N/GaN N/GaN HEMT, which is in close proximity with previously published simulated results. A peak transconductance of 154 mS/mm is also estimated for a 1-/[micro]m gate-length device with aluminum concentration of 15% (FS), which is in close agreement with previously published measured data. A high cutoff frequency of 21.09 GHz was predicted for a 0.6-/[micro]m device with an A1 mole fraction of 0.5 (PR), thus showing the potential of AlGaN/GaN HEMTs for microwave applications. Index Terms--[Al.sub.m][Ga.sub.1-m]N/GaN HEMTs, current-voltage characteristics, cutoff frequency, drain conductance, strain relaxation, threshold voltage, transconductance, transit time.

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ~2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory. [ABSTRACT FROM AUTHOR]

The present work investigates key attributes of metal–ferroelectric–metal–insulator–semiconductor (MFMIS) cylindrical nanowire (NW) transistor through a physics-based analytical model. The proposed NW MFMIS negative capacitance model is developed by solving the baseline short channel NW model coupled with one-dimensional Landau's equation while considering the radial dependency of electric field in the ferroelectric, a key feature for NW architecture. Contrary to the expected behaviour of a short channel MOSFET, the analytical framework successfully captures the unconventional effects such as an increase in the threshold voltage, lowering of subthreshold swing, and a negative value of drain-induced barrier lowering with gate length downscaling in MFMIS cylindrical NW devices. Also, the impact of ferroelectric thickness, spacer induced polarization charge density, remnant polarization and coercive field on the unconventional short channel effects have been examined. The influence of different ferroelectric materials (Al–HfO2, Gd–HfO2, Y–HfO2, and HZO) on the extent of internal amplification has also been investigated. The developed model provides new insights into the functioning and optimization of NW MFMIS architecture for facilitating hysteresis-free high internal voltage amplification with sub-60 mV/decade swing. [ABSTRACT FROM AUTHOR]

The operation of reconfigurable field effect transistor (RFET) is governed by Schottky barrier, ungated regions as well as control and polarity gates. The inherent architecture of RFET, apart from lowering the effective drain bias, impedes the use of existing mobility extraction methodologies. In this brief, we propose a simple and effective methodology to evaluate the resistance offered by various regions, ascertain the effective drain bias across the un-gated transistor, and extract apparent low field mobility and its degradation coefficients in RFET. The developed analytical expressions for drain current (${I}_{{\text {DS}}}$) and transconductance (${g}_{m}$) of RFET are able to accurately predict current (${I}_{\text {DS}}$) - control gate (${V}_{\text {CG}}$), and ${g}_{m}$ – ${V}_{\text {CG}}$ characteristics. [ABSTRACT FROM AUTHOR]

The present work investigates the suitability of Ge junctionless (JL) transistors for subthreshold logic applications. Considering that Ge exhibits a higher degree of short channel effects due to its higher permittivity, a semi-analytical model is first developed to capture the potential distribution and electron concentration in double gate (DG) Ge JL transistors with underlap regions for subthreshold operation. The model accurately predicts threshold voltage, drain-induced barrier lowering and subthreshold swing in Ge-based DG JL transistors. The work is extended to evaluate the subthreshold drain current for n-type and p-type DG Ge JL devices and the approach is adapted to extract three key technology-dependent parameters for ultra-low-power (ULP) (subthreshold) operation. The technology-dependent parameters are then utilized to evaluate key performance metrics of a subthreshold inverter. The upper and lower output voltage swing values, logic threshold voltage, and gain of the subthreshold inverter agree reasonably well with the developed modeling framework. The impact of technology downscaling, from a 5 nm to 0.7 nm node, on the performance of DG Ge JL subthreshold inverter is investigated, and possible options to enhance gain are outlined. Transient analysis highlighting NOT, NAND and NOR logic functionality with subthreshold Ge JL transistors has been investigated. Apart from base device and circuit assessment, the work also investigates the sensitivity of key metrics on physical transistor dimensions, supply voltage and temperature. The work showcases the potential benefits of optimally designed ULP n-type and p-type metal–oxide–semiconductor Ge JL devices for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

In this work, we report on the single transistor latch phenomenon in junctionless transistors. In the latch condition, the device is unable to turn-off despite a reduction in gate bias. It is shown that impact ionization induced latch condition can occur due to an increase in drain bias, silicon film thickness, gate oxide thickness, and doping concentration. The latch phenomenon is explained in terms of generation-recombination rates, electrostatic potential, electric field distribution and product of current density and electric field (J·E). As latch condition is undesirable for dynamic memory applications, the work highlights the significance of (J·E) as a performance metric to avoid the junctionless transistor being driven into the latch mode. [ABSTRACT FROM AUTHOR]

In this work, we present purely device-dependent conditions for achieving hysteresis-free sub-60 mV/decade (HF-sub-60) current transition in metal–ferroelectric–insulator–semiconductor (MFIS) nanowire transistor. The proposed bias-independent conditions for HF-sub-60 operation are also verified through conventional bias-dependent capacitance matching. Optimal ranges of Tfe for achieving HF-sub-60 current transition are examined for 1) varying radii of nanowire; 2) three ferroelectric materials (Al-HfO2, hafnium zirconium oxide (HZO) and Y-HfO2); 3) nanowire and planar architectures; and 4) coercive field and remnant polarization variations. Furthermore, the impact of gate length scaling is incorporated into the developed model. The proposed methodology in this article provides new and detailed guidelines into the selection of device and process parameters, ferroelectric materials, and device topologies for facilitating high internal voltage amplification factor, improved subthreshold swing and hysteresis-free operation in MFIS transistors. [ABSTRACT FROM AUTHOR]

This article reports on logic and memory functionality of vertically stacked bidirectional junctionless (BiJL) transistor, which can be operated as nMOS or pMOS depending on the biases applied. An inverter can be realized with a single BiJL transistor. If a complement of inputs is available, then NAND, NOR, and XOR logic can also be realized through a single BiJL transistor. The thickness of separation oxide between n-type and p-type films can be utilized to either achieve hysteresis or the absence of the same. Results provide insights into device physics, operation, and showcase new viewpoints for designing logic and memory devices with vertically stacked JL architecture, thus achieving the desired functionality with a lesser number of transistors. [ABSTRACT FROM AUTHOR]

This paper reports on the detection of hydrogen (H2) gas by utilizing a gate-all-around nanowire (NW) junctionless (JL) transistor as a sensor. The effects of temperature and pressure are considered in the transduction process through a change in gate workfunction of palladium (Pd) gate after exposure to $H_{2}$ gas. The analysis is performed through TCAD simulations, and an analytical model is developed in the subthreshold regime of device operation at a relatively low drain bias of 0.5 V. The performance of the NW JL transistor gas sensor is evaluated through the OFF-current-based sensitivity ($S_{I}$) and sensitivity based on threshold voltage shift ($S_{V}$). The analytical model developed for $S_{I}$ and $S_{V}$ shows a very good consistency with simulation data. The anomalous behavior of threshold voltage with temperature in the NW JL transistor under the influence of $H_{2}$ gas is analyzed in detail. This paper predominantly focuses on utilizing the NW JL transistor for low-power gas sensing, specifically at low pressures (10−15–10−10 torr), for temperatures ranging from 250 to 450 K. Insights into physical mechanisms within the device due to the transduction process are highlighted for optimum sensing. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness (${T}_{\textsf {Shell}}$) of 2 nm yields maximum retention. An SD (${N}_{\mathrm {d}}$) of $10^{18}$ cm $^{-\textsf {3}}$ attains RT of ~5.5 s and ~630 ms at 27 °C and 85 °C, respectively, whereas higher ${N}_{\textsf {d}}$ ($10^{19}$ cm $^{-\textsf {3}}$ shows RT of ~13ms at 85 °C for ${L}_{\textsf {g}} = \textsf {200}$ nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of ~11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths. [ABSTRACT FROM AUTHOR]

In this paper, we report on the utility of pocket tunnel field-effect transistors (TFETs) for use as dielectric-modulated biosensor. It is shown that incorporation of a pocket doping in the source facilitates lateral as well as vertical tunneling, which allows biomolecules located at various positions within the cavity to cause a detectable shift in current–voltage characteristics. Considering realistic cases pertaining to varied locations of biomolecules within the cavity and low fill-in (50%) factor, pocket TFET shows enhanced sensitivity over conventional TFET, which can be further improved by lowering the pocket doping. Sensitivity of a pocket TFET maintains detectable values over a wide range of biomolecule locations within the cavity, thereby showing potential for next generation transistor-based biosensor. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

In this paper, we report on the influence of surface (donor and acceptor) states and interface charges on the formation of 2-D electron gas (2DEG) in MgZnO/ZnO heterostructure grown by sputtering. Donor and acceptor states alone cannot yield an order of magnitude higher value of 2DEG as observed by sputtering growth as compared to epitaxial techniques. While surface donor states are reported to govern the formation of 2DEG in epitaxially grown heterostructures, our simulations suggest a non-negligible contribution of surface acceptor states in the 2DEG density. In addition, the existence of interface charges due to high defect density along with appropriate values of donor and acceptor states is essential to accurately predict an order of magnitude higher 2DEG density grown by sputtering. This paper analyzes the distinct roles of donor and acceptor states along with interface charges in 2DEG formation and achieved values. [ABSTRACT FROM AUTHOR]

This paper reports on the potential benefits of a vertically stacked ${n}$ - and ${p}$ -type junctionless (JL) transistor physically decoupled through an intermediate oxide layer for dynamic memory application. The proposed topology enhances the retention time (RT) of capacitorless dynamic random access memory (1T-DRAM), with a significant improvement $(\sim \!\!\times 10^{3})$ compared with a conventional JL transistor with a doping (${N}_{\text{d}}$) of 1019 cm−3. The functionality of architecture as DRAM is based on physically decoupling the conduction region (top ${n}$ -type JL transistor) and storage region (bottom ${p}$ -type JL), while maintaining an electrostatic coupling between them. The charge stored in the ${p}$ -type JL determines RT, and also impacts the read currents, and thus, influences the sense margin of DRAM. Stacked JL (SJL) 1T-DRAM achieves a maximum RT of ~2.5 s for ${N}_{\text{d}} = 5 \times 10^{18}$ cm−3 and ~1 s for 1019 cm−3 with a gate length (${L}_{\text{g}}$) of 200 nm at 85 °C. Results demonstrate its functionality down to 20 nm. The enhanced DRAM metrics (better scalability and high RT) are attributed to optimal architecture due to the vertical stacking of ${n}$ - and ${p}$ -type regions. [ABSTRACT FROM AUTHOR]

This paper reports the significance of device architecture to enhance impact ionization (I.I.) resulting in steep increase in the current from OFF- to ON-state. Recognizing that the area over which I.I. occurs is a key factor governing impact generated power per unit volume in the semiconductor film, we use raised source/drain (RSD) architecture to achieve sub-60-mV/decade subthreshold swing (S-swing) in germanium (Ge) junctionless (JL) devices at drain bias ( ${V}_{\text {ds}}$ ) of 0.9 V. The performance of RSD Ge JL device is compared with double-gate Ge JL transistor to highlight the occurrence of subthermal S-swing <5 mV/decade in RSD topology. The impact of band-to-band tunneling (BTBT) on the switching characteristics shows that RSD JL device with relatively thicker side oxide can effectively suppress BTBT while enhancing I.I. The influence of parasitic capacitance due to RSD regions and vertical doping gradient is also analyzed. Results highlight new viewpoints for the design of RSD Ge JL MOSFETs with channel doping $({N}_{\text {ch}}) \ge {5}\times {10}^{18}$ cm−3 to facilitate sharp current transition. [ABSTRACT FROM AUTHOR]

In this letter, we report on achieving significantly high (~ 6\times ) sheet charge density (ns) in MgZnO/CdZnO heterostructure, as compared with that in MgZnO/ZnO, at lower Mg ( \le 0.15 ) compositions in barrier MgZnO layer, with both heterostructures grown by dual ion beam sputtering technique. Buffer CdZnO and barrier MgZnO layers are probed separately to investigate carrier density in defect prone sputtered layers. Capacitance-voltage measurement and temperature-dependent Hall measurement confirm the presence of quantum confined carrier density at barrier-buffer interface, suggesting that the enhancement in carrier densities in the heterostructure over individual layers is probably due to the formation of 2-D electron gas (2-DEG). [ABSTRACT FROM PUBLISHER]

In this paper, we present a feasibility assessment of tunneling and accumulation mode p-type transistor architectures for use as dielectric-modulated biosensors. The performance of devices is compared through the estimation of the change in electrical characteristics between Iris antigen (bioreceptor) and anti-Iris antigen (target biomolecule) for a partially filled cavity. While tunnel field-effect transistors (TFETs) achieve higher sensitivity when biomolecules are positioned at the source–channel junction, the sensitivity rapidly diminishes when biomolecules are located away from the tunneling junction and, thus, severely limits their utility. Although accumulation mode field-effect transistors (AMFETs) also exhibit location-dependent sensitivity degradation, they show higher sensitivity values in comparison to the TFET for biomolecule layer located away from the source–channel junction. Furthermore, the application of back bias (~1 V) significantly improves the sensitivity (>8) for 40% filled cavity of p-type AMFET biosensors for all locations in the dielectric cavity. As higher sensitivity values over a wider biomolecule location are desirable, an AMFET performs better in comparison to the TFET cavity-modulated biosensor. This paper presents a systematic analysis, highlighting the benefits and limitations of each device for biosensing applications. Results highlight new viewpoints and insights in the design of AMFET-based cavity-modulated biosensors. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the impact of gate-source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for sub-threshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration (1018 cm-3). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs. [ABSTRACT FROM AUTHOR]

This paper demonstrates the use of doublegate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping (Nd) ≤ 1018 cm-3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm-3). RT of ~2.5 s at 85 °C and ~4.5 s at 27 °C is achieved for gate length (Lg) of 400 nm with Nd = 1017 cm-3 which reduces to ~90ms at 85 °C for Lg = 25 nm. This paper discusses the storage volume (Lg x film thickness for a fixed volume with width of 1 µm) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]

In this paper, we report on the reduction of the off-state band-to-band tunneling (BTBT) while maintaining sub-60 mV/decade switching in Germanium (Ge) Junctionless (JL) transistor through well-calibrated simulations. Recognizing the product of current density ( J ) and electric field ( E ) to be the key generic parameter governing device optimization, it is shown that a device with thicker film operated at lower drain bias ( V\text {ds} ) can sustain impact ionization and limit BTBT, thereby balancing the conflicting requirements of J\cdot E for tunneling and impact ionization. An optimal workfunction and gate-to-drain underlap of 5 nm in Ge JL MOSFET can further suppress BTBT while achieving a subthreshold swing of ~5 mV/decade with nearly four decades of steep current transition at the threshold voltage along with a low off-current ( \text 10^\text -10$}}\text{A}$ ) at {V}_{\text {ds}} = \text {0.9} V. Results highlight new viewpoints for the design optimization of steep-switching Ge JL MOSFETs. [ABSTRACT FROM PUBLISHER]

In this paper, we develop a generic analytical model for 2-D electron gas (2DEG) density ( \mathrmn\mathrm{s}) and threshold voltage ( \mathrmV \mathrm{\scriptscriptstyle OFF}) of a fully strained graded ZnO-based heterostructure with a cap layer. The model is based on the continuity of electric field at the interfaces of different layers, dominant piezoelectric and spontaneous polarization components in different layers, Mg composition, and layer thickness. The generic model can be reduced to a simplified bilayer structure for calculating \mathrmn\mathrm{s} and \mathrmV \mathrm{\scriptscriptstyle OFF} . Results show that the graded heterostructure can result in higher values of 2DEG density and \mathrmV \mathrm{\scriptscriptstyle OFF} (absolute values) compared to the bilayer structure. A careful optimization of the structure is required to achieve a trade-off between \mathrmn\mathrm{s} and \mathrmV \mathrm{\scriptscriptstyle OFF} . An analytical expression of polarization charge density at buffer–barrier interface to better fit the experimental data available in the literature is also proposed. The model will be suitable for the design optimization of 2DEG density and \mathrmV \mathrm{\scriptscriptstyle OFF} for ZnO-based heterostructures. [ABSTRACT FROM PUBLISHER]

We report dual ion beam sputtering fabrication of an Al/ZnO/Al memristor displaying forming-free bipolar resistive switching characteristics with memristive behavior without necessitating any postprocessing steps. A nearly amorphous ZnO thin film and an appropriate concentration of oxygen vacancies play a significant role in imparting forming-free, stable, and reliable behavior to memory cells. Besides, sufficient non-lattice oxygen ions in the film play a crucial role in the resistive switching process. The AlOx interface layer is observed to strongly affect the switching mechanism in the memory device by altering the barrier at the Al/ZnO interface. The device shows stable switching behavior for >250 cycles with good retention and stable set/reset voltages. [ABSTRACT FROM AUTHOR]

In this paper, we report on the anomalous behavior of threshold voltage ( V \sf th) with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage (dV \sf th /dT) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, V \sf th reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and V \sf th reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV \sf th /dT values in JL devices. [ABSTRACT FROM AUTHOR]

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( L_ \text gap) between the gates, and an underlap region ( L\text {un}) between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of L\text {gap} at 85 °C, which can be further improved to ~600 ms with the introduction of L\text {un} . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation. [ABSTRACT FROM PUBLISHER]

In this paper, we report on the prospect of achieving very high values ( \geq 10^13 cm ^-2 ) of 2-D electron gas (2-DEG) density in ZnO-based heterostructures through buffer layer engineering. A physics-based analytical model is developed and utilized to demonstrate up to 25\times higher 2-DEG values in MgZnO/CdZnO as compared with that in the MgZnO/ZnO heterostructure at lower Mg composition of 0.10 in barrier layer. It is shown that a lower spontaneous polarization in buffer layer due to more electronegative Cd and higher lattice constant of CdZnO, which introduces tensile piezoelectric strain in the barrier layer, favorably add up, and increase polarization difference at barrier-buffer interface, which eventually enhances 2-DEG density. This paper demonstrates new opportunities to effectively utilize buffer layer properties to significantly improve the 2-DEG sheet density (~ 4 \times 10^{\mathrm { {13}}} cm ^{\mathrm { {-2}}}$ ) in ZnO heterostructures. [ABSTRACT FROM AUTHOR]

In this paper, we propose and evaluate the feasibility of transconductance-to-current ratio ( g\mathrm {{m}}/I\mathrm {{ds}} ) as a sensing metric for a tunnel field-effect transistor (TFET)-based dielectric modulated biosensor. Focusing on the enhancement of the values of g\mathrm {{m}}/I\mathrm {{ds}} and current ratio at lower current levels to signify the presence of biomolecules in the dielectric cavity of TFET biosensor, the metric can be used not only for sensitivity but also for selectivity as the current ratio changes appreciably for the three different types of biomolecules, namely, Streptavidin, Biotin, and APTES. The g\mathrm {{m}}/I\mathrm {{ds}} extraction takes into account the operation at low power consumption, i.e., in the subthreshold region, which is most sensitive for biomolecule detection. The sensing methodology is governed by the location of the biomolecules within the cavity, and is less dependent on the fill-in factor. This paper highlights new opportunities to identify the sensing metric in TFET-based dielectric modulated biosensors. [ABSTRACT FROM PUBLISHER]

We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time (RT) of $\sim 1.5$ s at 85 °C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125 °C). [ABSTRACT FROM PUBLISHER]