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We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

To enable heterogeneous integration of InGaAs based transistors with Si complementary metal-oxide-semiconductor (CMOS) devices, metal contacts to n+-InGaAs need to have high thermal stability for CMOS process compatibility and ultra-low contact resistance to achieve good device performance. In this work, n+-InGaAs contacts with ultra-low contact resistivity pc based on refractory metals such as molybdenum (Mo) were realized. Use of refractory metal contacts achieves good thermal stability. An improved process that eliminates oxide between the metal and n+-InGaAs by using an in situ Ar+-plasma treatment prior to metal deposition achieves ultra-low pc. Furthermore, a nano-scale transmission line method (nano-TLM) structure with significantly reduced parasitic leakage was designed and fabricated to improve the pc extraction accuracy. The improved test structure introduces a SiO2 isolation layer between Mo and InGaAs outside the active or mesa region to eliminate a parallel leakage path that is present in other nano-TLM structures reported in the literature. [ABSTRACT FROM AUTHOR]

We report the temperature-dependent operation of back-end-of-line (BEOL) compatible amorphous indium-gallium-zinc-oxide (${a}$ -IGZO) ferroelectric thin-film transistors (FeTFTs) with a large memory window (MW) more than 3 V. Our ${a}$ -IGZO FeTFTs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) stru- cture with Zr-doped HfO2 (HZO) as the ferroelectric layer. Characteristics of ${a}$ -IGZO FeTFTs are investigated in the temperature range of −40 °C to 100 °C. We found that: Firstly, the remanent polarization (${P}_{\text {r}}$) of the HZO film increases with $2{P}_{\text {r}}$ from $\sim 35~ {\mu }\text{C}$ /cm2 at −40 °C to $\sim 40~ {\mu }\text{C}$ /cm2 at 100 °C. Secondly, enhancement in MWs at high temperatures is observed, achieving MWs larger than 3.5 V when the temperature is higher than 60 °C. Thirdly, for the threshold voltage (${V}_{\text {TH}}$) at high temperatures, there is a competition between the negative shift caused by higher carrier concentration in the ${a}$ -IGZO channel and positive shift due to the charge trapping at the floating gate in the MFMIS structure. This could be explored to realize good ${V}_{\text {TH}}$ stability. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ($\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing (SS) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage (${V}_{\text {TH}}$), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V. [ABSTRACT FROM AUTHOR]

We investigate the effect of channel layer thickness on effective mobility (μeff) in the sub-10-nm regime of amorphous indium–gallium–zinc–oxide thin-film transistors (α-IGZO TFTs). TFT devices with extremely scaled channel thickness tα-IGZO of 3.6 nm were realized, exhibiting low subthreshold swing (SS) of 74.4 mV/decade and the highest effective mobility μeff of 34 cm2/V ⋅ s at a carrier density NCarrier of ~ 5 × 1012 cm−2 for any kind of α-IGZO TFTs having sub-10-nm tα-IGZO. No significant degradation of μeff is observed as α-IGZO thickness reduced from 6 to 3.6 nm. By scaling down the channel length LCH to 38 nm, high extrinsic transconductance (Gm, max) of 125 μs/μm (at VDS of 1 V) and ON-state current ION of 350 μA/μm at VGS – VT of 3 V with VDS of 2.5 V are achieved. [ABSTRACT FROM AUTHOR]

We report high performance amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transis- tors (TFTs) with 10 nm atomic-layer-deposited HfO2 as the gate dielectric, achieving subthreshold swing (SS) of 70.2 mV/decade, high effective mobility (μeff) of 55.3cm2/V⋅s at an inversion carrier density (Ninv) of 5 × 1012 cm−2, and large ION/IOFF of > 109. Furthermore, very good device-to-device uniformity has been confirmed by the statistical distribution of SS and maximum transconductance (Gm, max) measured from 20 pristine TFT devices. This a-IGZO TFT has immense potential for the ultrafast and low power electronic devices for next-generation cost-effective emissive display, image sensing, and hardware for artificial intelligence (AI). [ABSTRACT FROM AUTHOR]

Germanium–tin (GeSn) p-channel fin field-effect transistor (p-FinFET) was realized on a novel GeSn-on-insulator (GeSnOI) substrate. The high-quality GeSnOI substrate was formed using direct wafer bonding technique and was layer-transferred from a 300-mm GeSn/Ge/Si donor wafer. Material quality was examined using atomic force microscopy, high-resolution transmission electron microscopy, Raman spectroscopy, and high-resolution X-ray diffraction. The fabricated GeSn p-FinFETs exhibit a small subthreshold swing (${S}$) of 79 mV/decade at ${V}_{\text {DS}}$ of −0.05 V (by a device with ${L}_{\text {CH}}$ of 200 nm and ${W}_{\text {Fin}}$ of 30 nm), good control of short channel effects, and high intrinsic transconductance (${G}_{m,\text {int}} = 702\,\,\mu \text {S}/\mu \text{m}$ at ${V}_{\text {DS}}$ of −0.5 V for ${L}_{\text {CH}}$ of 80 nm). Low-temperature mobility analysis was performed on the GeSn p-FinFETs. High effective hole mobility ($\mu _{\text {eff}}$) (210 cm2/ $\text {V}\cdot \text {s}$ at 290 K and 398 cm2/ $\text {V}\cdot \text {s}$ at 5 K) is achieved. The GeSn p-FinFETs presented in this paper exhibit the highest ${G}_{m,\text {int}}/{S}_{\text {sat}}$ at ${V}_{\text {DS}}$ of −0.5 V for all the reported GeSn p-FETs to date. [ABSTRACT FROM AUTHOR]

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- \mu \textm thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than 2 \times 10^7 cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a \delta -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of \sim 450 ~\mu \textS/ \mu \textm at V D of 0.5 V. The peak effective mobility ( \mu \text {eff} ) in a device with a channel length of 20 \mu \textm device channel was ~3700 cm2/ \textV \cdot \texts . [ABSTRACT FROM AUTHOR]

Integration of InxGa1–xAs n-MOSFETs and SiyGe1–y p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics. [ABSTRACT FROM PUBLISHER]

We report on the growth of an In0.30Ga0.70As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 µm thick buffer comprising a Ge layer, a GaAs layer and an In- AlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 107 cm-2 with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 µm long channel length transistors are fabricated from the wafer with IDS of 70 µA/µm and gm of above 60 µS/µm, demonstrating the high quality of the grown materials. [ABSTRACT FROM AUTHOR]

Angiolipoma is one of the rare variant of lipoma. This benign tumour consists of both fatty and vascular elements. It mostly occur in the trunk and extremities and is uncommon in head and neck region. Angiolipoma is classified as infiltrating and non- infiltrating types. Among all neoplasms of the oral cavity, lipomas account for 1 to 5% and the incidence of angiolipoma is 5 to 17% in it. There is no sex predilection for this tumour. It is classified as infiltrative and non-infiltrative type. Surgical excision is the method to be considered for both the types of angiolipoma, however the infiltrating type recurs post-surgery. We report a rare case report of 55-year-old female with non-infiltrating angiolipoma of the hard palate mimicking a mucocele treated by surgical excision with no signs of recurrence and good wound healing after three months follow up with minimal scar formation. [ABSTRACT FROM AUTHOR]

We demonstrate Ge 0.95 Sn 0.05 p-channel gate-all-around field-effect transistors (p-GAAFETs) with sub-3 nm nanowire width ( W NW ) on a GeSn-on-insulator (GeSnOI) substrate using a top-down fabrication process. Thanks to the excellent gate control by employing an aggressively scaled nanowire structure, Ge 0.95 Sn 0.05 p-GAAFETs exhibit a small subthreshold swing (SS) of 66 mV/decade, a decent on-current/off-current ( I ON / I OFF ) ratio of ∼1.2 × 10 6 , and a high-field effective hole mobility ( μ eff ) of ∼115 cm 2 /(V s). In addition, we also investigate quantum confinement effects in extremely scaled GeSn nanowires, including threshold voltage ( V TH ) shift and I OFF reduction with continuous scaling of W NW under 10 nm. The phenomena observed from experimental results are substantiated by the calculation of GeSn bandgap and TCAD simulation of electrical characteristics of devices with sub-10 nm W NW . This study suggests Ge-based nanowire p-FETs with extremely scaled dimension hold promise to deliver good performance to enable further scaling for future technology nodes.

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an I ON /I OFF ratio of more than 10 6 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

We report the first monolithic integration of InGaAs channel field-effect transistors with InGaAs/GaAs multiple quantum wells (MQWs) lasers on a common platform, achieving a milestone in the path of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers used for realizing transistors and lasers were grown epitaxially on the Ge substrate using molecular beam epitaxy (MBE). A Si-CMOS compatible process was developed to realize InGaAs n-FETs with subthreshold swing SS of 93 mV/decade, I ON /I OFF ratio of more than 4 orders of magnitude with very low off-state leakage current, and a peak effective mobility of more than 2000 cm 2 /V·s. In addition, fabrication process uses a low overall processing temperature (≤ 400 °C) to maintain the high quality of the InGaAs/GaAs MQWs for the laser. Room temperature electrically-pumped lasers with a lasing wavelength of 1.03 µm and a linewidth of less than 1.7 nm were realized.