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A 24 GHz self-calibrated all-digital frequency-modulated continuous-wave (FMCW) synthesizer is presented in this article. A multi-bank digitally controlled oscillator (DCO) is employed to provide adequate frequency tuning range and high frequency resolution. A full background self-calibration scheme is proposed to linearize the DCO tuning curve for highly linear and fast chirp generation. An overlap compensator based on an adaptive lookup table (LUT) is utilized to eliminate the frequency overlaps between adjacent DCO tuning bands. The compensation words in the LUT are altered by least-mean-square (LMS) algorithm for robust and precise matching. A ramp tracker, which features real-time ramp tracking with zero steady-state phase error, is employed to estimate and stabilize the frequency ramp. Implemented in 40 nm bulk CMOS, the FMCW synthesizer prototype consumes 28 mW with a 0.26 mm2 core area. The maximum chirp bandwidth is 3.2 GHz, corresponding to 13.33% of the center frequency. Measurement results show that the root-mean-square (RMS) frequency error is reduced by 1/10 with self-calibration after 2 ms convergence time. The maximum chirp slope is up to 320 MHz/ $\mu \text{s}$ with 309 kHz RMS frequency error. The minimum RMS frequency error is 7.35 kHz under 5 MHz/ $\mu \text{s}$ chirp slope, corresponding to 0.0002% of the chirp bandwidth. [ABSTRACT FROM AUTHOR]

A physics-based equivalent-circuit model for on-chip symmetric transformers is presented with all the model elements driven from fabrication specifications. Two extra coupled transformer loops are used for each coil to model the parameters of skin effect, proximity effect, and reflective effect of the substrate eddy current, respectively. Model accuracy under free space is first demonstrated using an electromagnetic field solver without considering substrate loss. Several sets of transformers were fabricated on a standard 0.18-[micro]m 1P8M RF CMOS technology to further verify the accuracy and scalability of the proposed model. By careful comparison of S-parameters, coil inductance, quality factor, coupling coefficient, and maximum available gain between measured data and simulated data, model accuracy, and scalability are verifed over a wide range of geometry configurations. Index Terms--Baluns, eddy current, equivalent circuit, physical model, transformers.

We report on an effective way of using a patterned ground shield (PGS) to enhance the Q factor of on-chip spiral inductors. We fabricated PGS inductors using both 0.18 [micro]m and 0.35 [micro]m CMOS processes, with M1 and poly strip PGSs, respectively. The strip width and spacing of the PGSs are [W.sub.g] = 0.8 [micro]m and [S.sub.g] = 0.4.3 [micro]m, with metal thicknesses of [t.sub.p] = {0.54.0.2} [micro]m in the 0.18 [micro]m process, and [t.sub.p] {0.6, 0.3} [micro]m in the 0.35 [micro]m process. The separation distance D between PGS and top metal layer is different in both processes. We found that the Q factor degradation of inductors at high temperatures can be effectively compensated by using PGS. Among all geometric parameters of a PGS in the 0.18 [micro]m process, the parameter D is the critical factor for the shielding effectiveness, and M1 PGS is much more efficient than poly strip PGS in improving the inductor performance over the temperature range of 298 K to 358 K. However, in the 0.35 [micro]m process the latter is better than the former. Index Terms--Pattern ground shield (PGS) inductors, performance enhancement, Q factor, shielding effectiveness, temperature.

A 12-bit 0.5–2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The DPC is designed and fabricated in 40-nm CMOS technology, which occupies a chip area of 0.04 mm2 and consumes 18.3 mW from a 1.3-V supply voltage. Operating in a frequency range from 0.5 to 2.4 GHz, the DPC demonstrates a peak integral nonlinearity (INL) of 0.65° and a peak differential nonlinearity (DNL) of 0.25°. [ABSTRACT FROM AUTHOR]

This letter presents a CMOS reverse received signal strength indicator (reverse-RSSI) based logarithmic power detector (PD). A capacitor attenuation array and unbalanced source-coupled rectifiers are utilized to constitute the reverse-RSSI architecture, which greatly increases the maximum detectable power. Two auxiliary capacitors in the rectifier are introduced to improve linearity at high input power dramatically. The PD with 0.4–5-GHz operating frequency can be fully integrated and has stable and reliable performance according to multiple tests. Measurement results show that the maximum detectable power achieves +35 dBm and dynamic range reaches 45 dB with ±1-dB linearity error. The proposed PD is implemented in a standard 180-nm CMOS process with 0.085 mm2 core area. The total static power consumption is 0.78 mW with a 3.3-V supply voltage. [ABSTRACT FROM AUTHOR]

A high-resolution digitally controlled oscillator (DCO) for frequency-modulated continuous-wave radar applications is presented in this brief. The proposed DCO utilizes a variable inductor and linearization correction technique, and cooperates with the multi-stage frequency multipliers to achieve frequency sources at 2.9, 5.8, and 11.6 GHz simultaneously on a single chip. The demonstration of the proposed DCO and frequency multipliers was fabricated in 1P10M 40-nm CMOS technology. Measurement results show that the frequency resolution of the DCO achieves 0.73 to 1.3 kHz over a frequency range of 16.8%, from 2.5 to 2.96 GHz. The phase noise at 1-MHz frequency offset is −127.3 dBc/Hz with 15-mW power consumption. The chip occupies 0.73 mm2, while the proposed DCO occupies a core area of 0.31 mm2. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an interference‐resilient receiver front end for body channel communication, which uses the human body as the signal transmission medium in the band of 40 to 60 MHz. To tackle strong out‐of‐band interference resulting from the human body antenna effect, a series N‐path filter–based balun preceding a low‐noise amplifier is proposed to improve the frequency modulation radio interference suppression and realize single‐to‐differential transformation of input body channel communication signals. Besides, an enhanced harmonic rejection with combination of a series N‐path filter and a harmonic rejection passive mixer using 8‐phase 12.5% duty‐cycle clocks as local oscillator is presented. The transconductance amplifier sharing is used to reduce the power consumption of the mixer. Fabricated in a standard 0.18‐μm complementary metal‐oxide‐semiconductor process, the proposed receiver front end occupies an area of 780 × 660 μm2 including pads. Operating at 50 MHz, the front end consumes 1.35 mA from a 1.8‐V supply and achieves a maximum gain of 50.5 dB with a noise figure of 11.2 dB, 28.5 dB frequency modulation interference suppression at the second‐order harmonic rejection, and 53.9 dB at the third‐order harmonic rejection. This paper presents an interference‐resilient receiver front end for body channel communication in the band of 40 to 60 MHz. To tackle strong out‐of‐band interferences resulting from the human body antenna effect, a series N‐path filter–based balun preceding a low‐noise amplifier is proposed to improve the frequency modulation radio interference suppression and realize single‐to‐differential transformation. Operating at 50 MHz, the front end consumes 2.4 mW and achieves 28.5 dB FM interference suppression at the second‐order harmonic rejection and 53.9 dB at the third‐order harmonic rejection. [ABSTRACT FROM AUTHOR]

ABSTRACT A fully CMOS integrated low TX noise UHF RFID digital transmitter with tunable directional coupler is proposed. The transmitter decreases the AM noise density to −144.6 dBc/Hz at 10 kHz offset by eliminating noisy conventional analog components and optimizing LO chain. The tunable transformer-based directional coupler which is feasible for CMOS integration exhibits high isolation performance of −55 dB over the entire band. The transmitter with quadrature DPA structure supports DSB/SSB/PR-ASK modulation, and with the directional coupler, it achieves 22.8 dBm peak power with drain efficiency of 37.8%. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1750-1756, 2016 [ABSTRACT FROM AUTHOR]

A highly reconfigurable merged analog baseband (MABB) with not only tunable bandwidth (BW), gain, and order but also reconfigurable power, noise, and linearity is proposed for multistandard integrated wireless receivers in this brief. The MABB could arrange the total gain to different stages for noise and linearity tradeoffs by introducing the merged biquad topology. To save power, the operational amplifier (Opamp) for the proposed MABB can reduce the GBW, as long as it meets the GBW requirement for different BW, gain, and order. A flexible power-efficient high-GBW Opamp with an adaptive common-mode bias circuit is also proposed for the eighth-order active-RC MABB. The proposed MABB covers a cutoff frequency range from 200 kHz to 20 MHz, whereas the gain could be tuned between 0 and 72 dB. The proposed highly reconfigurable MABB is suitable for multistandard integrated wireless receivers. [ABSTRACT FROM PUBLISHER]

This article presents a 2-GHz fully-differential CMOS power amplifier (PA) fabricated in a standard 0.35-μm RF CMOS process. Virtual grounds are introduced at both drive-stage and output-stage transistors' sources of the two-stage differential PA, which guarantees a stable reference ground and thus improves the PA performance. A performance of 15-dB gain, 26.6 dBm Pout, and 26% PAE is achieved. At 15 dBm Pout, the ACPR1 and ACPR2 are -35.3 and -66.3 dBc, respectively. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2780–2784, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22849 [ABSTRACT FROM AUTHOR]

A fully integrated ultrawideband (UWB) bipolar cascode with metal oxide semiconductor field effect transistor (BiFET) mixer using standard commercial 0.35-μm silicon germanium bipolar complementary metal oxide semiconductor technology was first proposed and fabricated in this study. This presented BiFET mixer using bipolar junction transistor as the transconductor stage and metal oxide semiconductor field effect transistor as the switch stage to achieve noise power and linearity trade-off. This 3–5-GHz UWB mixer achieves a conversion gain of 4.5 ± 0.5 dB at the designed band. The mixer core draws a current of 2.5 mA from a supply voltage of 3 V, while consumes chip area of 0.9 × 0.9 mm2. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 965–968, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22305 [ABSTRACT FROM AUTHOR]

SOI technology is now emerging as a mature technology applied in the analog IC design, which necessities an accurate model to describe distortion effects. In this paper a compact transistor model is proposed for distortion analysis of fully depleted SOI MOSFET operating in strong inversion regime. In the model, both short channel effects and self-heating effect (unique to SOI due to the buried oxide) are considered. To obtain a concise and accurate model, an approximation method is developed to determine the dominant physical effects in distortion analysis. The model agrees well with the experimental data. [Copyright &y& Elsevier]

This letter proposes a miniature CMOS stacked spiral-coupled (SSC) directional coupler for a fully integrated CMOS transceiver to isolate the large transmit power from the transmitter to the receiver. It consists of two 90 ^\circ-rotated center-aligned SSC coils. The path center of one coil is aligned to the gap center of the other coil. The grounded secondary coil plays a role of ground shielding for reducing the insertion loss. Two capacitors are utilized for tuning the center frequency and isolation level. Fabricated in a standard CMOS process, it achieves an isolation of -67 dB, an insertion loss of -0.8 dB, and a coupling of -16.1 dB and only occupies \0.3 \times \0.3\ \mm^2 of silicon area. To the authors' knowledge, this is the first CMOS directional coupler at the UHF band, with the smallest form factor when compared with other implementations of directional couplers. [ABSTRACT FROM PUBLISHER]

Characteristics of symmetrical spiral inductor in differential mode is studied and optimized in this work. The characteristics of interest include inductor value, quality factor, peak frequency and self-resonance frequency. Both single-layer and double-layer inductor using top metals are characterized. Inductor excited in differential mode and single-ended mode are characterized for comparison. The optimized symmetrical spiral inductors are fabricated in standard digital 0.35 μm CMOS process. Experimental results show 60–100% improvement of quality factor and peak frequency, meanwhile 10–20% improvement of self-resonance frequency by exciting the symmetrical spiral inductors in differential mode compared with single-ended mode. To further validate the characterized inductor, the differential spiral inductors are adopted in optimizing low power and low phase noise fully integrated 2.4 GHz voltage-controlled oscillator (VCO). The designed VCO achieved phase noise of more than -105 dBc/Hz at 100 kHz offset with approximately 4.5 mA at 3.0 V supply. [Copyright &y& Elsevier]