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A memristor array has emerged as a potential computing hardware for artificial intelligence (AI). It has an inherent memory effect that allows information storage in the form of easily programmable electrical conductance, making it suitable for efficient data processing without shuttling of data between the processor and memory. To realize its full potential for AI applications, fine-tuning of internal device dynamics is required to implement a network system that employs dynamic functions. Here, we provide a perspective on multicationic entropy-stabilized oxides as a widely tunable materials system for memristor applications. We highlight the potential for efficient data processing in machine learning tasks enabled by the implementation of "task specific" neural networks that derive from this material tunability. [ABSTRACT FROM AUTHOR]

Analog compute‐in‐memory (CIM) systems are promising candidates for deep neural network (DNN) inference acceleration. However, as the use of DNNs expands, protecting user input privacy has become increasingly important. Herein, a potential security vulnerability is identified wherein an adversary can reconstruct the user's private input data from a power side‐channel attack even without knowledge of the stored DNN model. An attack approach using a generative adversarial network is developed to achieve high‐quality data reconstruction from power leakage measurements. The analyses show that the attack methodology is effective in reconstructing user input data from power leakage of the analog CIM accelerator, even at large noise levels and after countermeasures. To demonstrate the efficacy of the proposed approach, an example of CIM inference of U‐Net for brain tumor detection is attacked, and the original magnetic resonance imaging medical images can be successfully reconstructed even at a noise level of 20% standard deviation of the maximum power signal value. This study highlights a potential security vulnerability in emerging analog CIM accelerators and raises awareness of needed safety features to protect user privacy in such systems. [ABSTRACT FROM AUTHOR]

Network features found in the brain may help implement more efficient and robust neural networks. Spiking neural networks (SNNs) process spikes in the spatiotemporal domain and can offer better energy efficiency than deep neural networks. However, most SNN implementations rely on simple point neurons that neglect the rich neuronal and dendritic dynamics. Herein, a bio‐inspired columnar learning network (CLN) structure that employs feedforward, lateral, and feedback connections to make robust classification with sparse data is proposed. CLN is inspired by the mammalian neocortex, comprising cortical columns each containing multiple minicolumns formed by interacting pyramidal neurons. A column continuously processes spatiotemporal signals from its sensor, while learning spatial and temporal correlations between features in different regions of an object along with the sensor's movement through sensorimotor interaction. CLN can be implemented using memristor crossbars with a local learning rule, spiking timing‐dependent plasticity (STDP), which can be natively obtained in second‐order memristors. CLN allows inputs from multiple sensors to be simultaneously processed by different columns, resulting in higher classification accuracy and better noise tolerance. Analysis of networks implemented on memristor crossbars shows that the system can operate at very low power and high throughput, with high accuracy and robustness to noise. [ABSTRACT FROM AUTHOR]

In analog in‐memory computing systems based on nonvolatile memories such as resistive random‐access memory (RRAM), neural network models are often trained offline and then the weights are programmed onto memory devices as conductance values. The programmed weight values inevitably deviate from the target values during the programming process. This effect can be pronounced for emerging memories such as RRAM, PcRAM, and MRAM due to the stochastic nature during programming. Unlike noise, these weight deviations do not change during inference. The performance of neural network models is investigated against this programming variation under realistic system limitations, including limited device on/off ratios, memory array size, analog‐to‐digital converter (ADC) characteristics, and signed weight representations. Approaches to mitigate such device and circuit nonidealities through architecture‐aware training are also evaluated. The effectiveness of variation injection during training to improve the inference robustness, as well as the effects of different neural network training parameters such as learning rate schedule, will be discussed. [ABSTRACT FROM AUTHOR]

Memristive devices have demonstrated rich switching behaviors that closely resemble synaptic functions and provide a building block to construct efficient neuromorphic systems. It is demonstrated that resistive switching effects are controlled not only by the external field, but also by the dynamics of various internal state variables that facilitate the ionic processes. The internal temperature, for example, works as a second‐state variable to regulate the ion motion and provides the internal timing mechanism for the native implementation of timing‐ and rate‐based learning rules such as spike timing dependent plasticity (STDP). In this work, it is shown that the 2nd state‐variable in a Ta2O5‐based memristor, its internal temperature, can be systematically engineered by adjusting the material properties and device structure, leading to tunable STDP characteristics with different time constants. When combined with an artificial post‐synaptic neuron, the 2nd‐order memristor synapses can spontaneously capture the temporal correlation in the input streaming events. [ABSTRACT FROM AUTHOR]

We present TAICHI, a general in-memory computing deep neural network accelerator design based on RRAM crossbar arrays heterogeneously integrated with local arithmetic units and global co-processors to allow the system to efficiently map different models while maintaining high energy efficiency and throughput. A hierarchical mesh network-on-chip is implemented to facilitate communication among clusters in TAICHI to balance reconfigurability and efficiency. Detailed deployment of the different circuit components is discussed, and the system performance is estimated at several technology nodes. The heterogeneous design also allows the system to accommodate models larger than the on-chip storage capability. [ABSTRACT FROM AUTHOR]

The advances of neural recording techniques have fostered rapid growth of the number of simultaneously recorded neurons, opening up new possibilities to investigate the interactions and dynamics inside neural circuitry. The high recording channel counts, however, pose significant challenges for data analysis because the required time and computational resources grow superlinearly with the data volume. Herein, the feasibility of real‐time reconstruction of neural functional connectivity using a second‐order memristor network is analyzed. Spike‐timing‐dependent plasticity, natively implemented by the internal dynamics of the memristor device, leads to the successful discovery of temporal correlations between pre‐ and postsynaptic spikes of the simulated neural circuits in an unsupervised fashion. The proposed system demonstrates high classification accuracy under a wide range of parameter settings considering indirect connections, synaptic weights, transmission delays, connection density, and so on, and enables the capturing of dynamic connectivity evolutions. The influence of device nonideal factors on detection accuracy is systematically evaluated, and the system shows robustness to initial weight randomness, and cycle‐to‐cycle and device‐to‐device variations. The proposed method allows direct mapping of neural connectivity onto the artificial memristor network and can lead to efficient front‐end data analysis of high‐density neural recording systems and potentially directly coupled bioartificial networks. [ABSTRACT FROM AUTHOR]

Stochastic Computing (SC) is a computing paradigm that allows for the low-cost and low-power computation of various arithmetic operations using stochastic bit streams and digital logic. In contrast to conventional representation schemes used within the binary domain, the sequence of bit streams in the stochastic domain is inconsequential, and computation is usually non-deterministic. In this brief, we exploit the stochasticity during switching of probabilistic Conductive Bridging RAM (CBRAM) devices to efficiently generate stochastic bit streams in order to perform Deep Learning (DL) parameter optimization, reducing the size of Multiply and Accumulate (MAC) units by 5 orders of magnitude. We demonstrate that in using a 40-nm Complementary Metal Oxide Semiconductor (CMOS) process our scalable architecture occupies 1.55mm2 and consumes approximately 167 μW when optimizing parameters of a Convolutional Neural Network (CNN) while it is being trained for a character recognition task, observing no notable reduction in accuracy post-training. [ABSTRACT FROM AUTHOR]

Memristors have emerged as transformative devices to enable neuromorphic and in‐memory computing, where success requires the identification and development of materials that can overcome challenges in retention and device variability. Here, high‐entropy oxide composed of Zr, Hf, Nb, Ta, Mo, and W oxides is first demonstrated as a switching material for valence change memory. This multielement oxide material provides uniform distribution and higher concentration of oxygen vacancies, limiting the stochastic behavior in resistive switching. (Zr, Hf, Nb, Ta, Mo, W) high‐entropy‐oxide‐based memristors manifest the "cocktail effect," exhibiting comparable retention with HfO2‐ or Ta2O5‐based memristors while also demonstrating the gradual conductance modulation observed in WO3‐based memristors. The electrical characterization of these high‐entropy‐oxide‐based memristors demonstrates forming‐free operation, low device and cycle variability, gradual conductance modulation, 6‐bit operation, and long retention which are promising for neuromorphic applications. [ABSTRACT FROM AUTHOR]

Abstract Background Cytotoxic drugs are non-selective between normal and pathological tissue, and this poses a challenge regarding the strategy for treatment of tumors. To achieve sufficient antitumor activity for colorectal carcinoma, optimization of the therapeutic regimen is of great importance. We investigated the ability of oxaliplatin long-circulating liposomes (PEG-liposomal L-oHP) to provide an improved therapeutic index of colorectal carcinoma. Results We determined that PEG- liposomes conjugated with cells at 2 h, with a mean fluorescence intensity that was enhanced upon extended induction time. The PEG-liposomal L-oHP induced a significant apoptotic response as compared with free L-oHP, 23.21% ± 3.38% vs. 16.85% ± 0.98%, respectively. Fluorescence imaging with In-Vivo Imaging demonstrated that PEG- liposomes specifically targeted tumour tissue. After intravenous injections of PEG-liposomal L-oHP or free L-oHP, the tumour volume suppression ratio was 26.08% ± 12.43% and 18.19% ± 7.09%, respectively, the percentage increased life span (ILS%) was 45.36% and 76.19%, respectively, and Bcl-2, Bax mRNA and protein expression in tumour tissue was 0.27-fold vs. 0.88-fold and 1.32-fold vs. 1.61-fold compared with free L-oHP, respectively. Conclusion The PEG-liposomal L-oHP exhibited a tendency to target tumour tissue and demonstrated a significantly greater impact on apoptosis compared to free oxaliplatin.

Self-limited and forming-free Cu-based CBRAM devices with a double Al2O3 atomic layer deposition layer (D-ALD) structure were developed. The proposed structure offers desirable properties such as forming free (${V}_{\textsf {forming}}={V}_{\textsf {SET}}$), self-limited resistive switching with very low programming current ~10 nA), high ON/ OFF ratio (> 100), and nonlinear ${I}$ – ${V}$ (NL $_{\textsf {read}}$ and NL $_{\textsf {SET}}$ ~ 10) at low resistance state. The outstanding performance of D-ALD devices was due to the HT-ALD layer that operates as both a diffusion barrier preventing over injection of Cu ions and a tunneling barrier enabling self-limited programming. [ABSTRACT FROM AUTHOR]

Neuromorphic systems using memristors as artificial synapses have attracted broad interest for energy-efficient computing applications. However, networks based on these purely passive devices can be affected by parasitic effects such as series resistance and sneak path problems. Here, we analyze the effects of parasitic factors on the performance of memristor-based neuromorphic systems. During vector-array multiplication, the line resistance can cause significant distortion of the output current and the activity of the corresponding neurons. An approach to compensate the line resistance effects based on an approximate model consisting of only few known parameters is proposed and shows excellent ability to capture the complex network behavior. During training and feature detection, the series resistance can cause significant degradation of the learned dictionary, with only a few dominant neurons being trained. Using a scaling factor based on the proposed simple model, these effects can be successfully mitigated, and the correct network operations can be restored. These results provide insight and practical measures on the parasitic effects for implementation of the neuromorphic system using memristor arrays. [ABSTRACT FROM PUBLISHER]

Reservoir computing systems utilize dynamic reservoirs having short-term memory to project features from the temporal inputs into a high-dimensional feature space. A readout function layer can then effectively analyze the projected features for tasks, such as classification and time-series analysis. The system can efficiently compute complex and temporal data with low-training cost, since only the readout function needs to be trained. Here we experimentally implement a reservoir computing system using a dynamic memristor array. We show that the internal ionic dynamic processes of memristors allow the memristor-based reservoir to directly process information in the temporal domain, and demonstrate that even a small hardware system with only 88 memristors can already be used for tasks, such as handwritten digit recognition. The system is also used to experimentally solve a second-order nonlinear task, and can successfully predict the expected output without knowing the form of the original dynamic transfer function. [ABSTRACT FROM AUTHOR]

The development of smart, scalable, and power efficient computers relies on innovative technologies that can distribute memory alongside processing, such as emerging neuromorphic computing and in-memory logic technologies. Here, a type of vertical 3-terminal oxide based nanoionic device capable of implementing heterosynaptic plasticity and nonvolatile Boolean logic simultaneously is demonstrated. The heterosynaptic plasticity endows the devices with facilely tunable synaptic kinetics via tailoring modulatory signals, which is shown to be crucial for achieving optimized learning scheme, therefore offering promising building blocks for neuromorphic computing. Furthermore, it is demonstrated that these heterosynaptic devices can simultaneously be utilized to implement nonvolatile Boolean logic with improved efficiency compared with existing approaches, therefore implying in-memory computing potentialities. The heterosynaptic devices with such multifunctionality thus hold great potential for next-generation non-von Neumann computing applications. [ABSTRACT FROM AUTHOR]