Search

Hardware Trojan is malicious tampering to the original circuit, which has become the most important security threat of integrated circuit. In order to ensure the safety and reliability of ICs, many hardware Trojan detection methods are proposed. As one of the formal verification methods, model checking can effectively detect the hardware Trojan in the design phase. Firstly, the working principle and process of model checking were described. Secondly, the research progress of hardware Trojan detection technology based on model checking was introduced. Finally, the bottlenecks faced by the current technology were pointed out and the potential research direction was discussed.

In this paper, a liquid crystal-modulated metastructure sensor (MS) is proposed that can detect the refractive index (RI) of a liquid and change the detection range under different applied voltages. The regulation of the detection range is based on the different bias states of the liquid crystal at different voltages. By changing the sample in the cavity that is to be detected, the overall electromagnetic characteristics of the device in the resonant state are modified, thus changing the position of the absorption peaks so that different RI correspond to different absorption peaks, and finally realizing the sensing detection. The refractive index unit is denoted as RIU. The range of the refractive index detection is 1.414–2.828 and 2.121–3.464, and the corresponding absorption peak variation range is 0.8485–1.028 THz and 0.7295–0.8328 THz, with a sensitivity of 123.8 GHz/RIU and 75.6 GHz/RIU, respectively. In addition, an approach to optimizing resonant absorption peaks is explored, which can suppress unwanted absorption generated during the design process by analyzing the energy distribution and directing the current flow on the substrate. Four variables that have a more obvious impact on performance are listed, and the selection and change trend of the numerical values are focused on, fully considering the errors that may be caused by manufacturing and actual use. At the same time, the incident angle and polarization angle are also included in the considered range, and the device shows good stability at these angles. Finally, the influence of the number of resonant rings on the sensing performance is also discussed, and its conclusion has guiding value for optimizing the sensing demand. This new liquid crystal-modulated MS has the advantages of a small size and high sensitivity and is expected to be used for bio-detection, sensing, and so on. All results in this work were obtained with the aid of simulations based on the finite element method. [ABSTRACT FROM AUTHOR]

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce $5.35\times $ power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications. [ABSTRACT FROM AUTHOR]

Electromagnetic (EM) side-channel analysis is a powerful attack for extracting secret information from cryptographic hardware implementations. Countermeasures have been proposed at the register-transfer level (RTL), layout level, and device level. However, existing EM radiation modeling and side-channel vulnerability mitigation methods do not consider the structural resilience of original designs, nor do they provide fine-grained security enhancements to those vulnerable submodules/components. These universal solutions may introduce unnecessary overheads on the circuit under protection and may not be optimized for individual designs. In this article, we propose a design/synthesis for side-channel security evaluation and optimization framework based on the ${t}$ -test evaluation results derived from RTL hardware implementations. While the framework apply to different side-channel leakage, we focus more on EM side channels. Supported by this framework, different RTL implementations of the same cryptographic algorithm will be evaluated for their side-channel resistance. In vulnerable implementations, submodules with the most significant side-channel leakages will be identified. Security design/synthesis rules will then be applied to these vulnerable submodules for security enhancements against side-channel attacks (SCAs). Experiments, including simulations and FPGA implementations on different AES designs, are performed to validate the effectiveness of the proposed framework as well as the security design/synthesis rules. [ABSTRACT FROM AUTHOR]

In order to achieve higher system performance, a digital calibration technique for the sub-channel mismatches of time-interleaved ADCs (TIADCs) is proposed in this paper. The sine-fit-based estimation algorithm is introduced to estimate the channel mismatches and a calibration algorithm is proposed to compensate for the mismatches. Subsequently, the genetic algorithm (GA) is firstly utilized to detect the mismatch errors of the outputs of sub-channels after frequency domain filtering. The detected offset error and gain error are then corrected by performing the calibration algorithm, and the time errors are corrected by fractional delay filters based on Farrow structure. The spurious-free dynamic range (SFDR) is enhanced from 19.69 dB to 108.12 dB, and the signal to noise and distortion ratio (SNDR) is enhanced from 16.02 dB to 97.63 dB. The proposed technique is further validated on the FPGA. Compared with existing calibration techniques, the proposed technique has the advantages of simple algorithm structure, low hardware resource consumption, and high calibration accuracy and can be applied to the calibration of high-resolution (18-bit) TIADCs for low-frequency inputs. [ABSTRACT FROM AUTHOR]

Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) that can be reconfigured to the desired functionalities, without manufacturing dedicated chips. Due to their programmable nature, FPGAs have been prevalent in the large majority of modern systems. This raises high demands for verifying the security of circuit implementations on FPGAs, since they are vulnerable to hardware trojans (HTs) that can be inserted through modified configuration files. In this article, we propose an on-chip security framework to ensure the trustworthiness of circuit implementations on FPGAs at runtime. The core of the framework is a time-to-digital converter (TDC)-based hardware security primitive that can be predeployed on FPGAs to verify whether the FPGA-based designs are tampered with or corrupted by HTs. The parameter-adjustable TDC sensor, which is the primary component of the primitive, is carefully designed, adjusted, and implemented, thus the TDC sensor can monitor the transient voltage fluctuations within FPGAs with a high resolution. Versus statistical data analysis, tiny abnormal variations introduced by the Trojan insertion and activation are distinguished. Experimental results on Xilinx Spartan-6 FPGAs demonstrate the effectiveness of the proposed TDC-based on-chip trust evaluation framework and HT detection method. [ABSTRACT FROM AUTHOR]

Side-channel analysis (SCA) attacks are major threats to hardware security. Upon this security threat, various countermeasures at different design layers have been proposed against SCA attacks. These approaches often introduce significant overheads and impose high requirements of side-channel security backgrounds to integrated circuit (IC) designers. In this article, we propose an automatic computer-aided design (CAD) tool that can be utilized to enhance the circuit resistance against electromagnetic (EM) SCA attacks. This new tool will guide security-driven placement and routing processes and can be seamlessly integrated into the modern IC design flow. The protected IC design will be resilient to SCA attacks with negligible area and power overheads. In order to develop this tool, we first investigate the root-cause of EM leakage at the layout level and mathematically demonstrate the feasibility of security-driven placement and routing through the EM leakage modeling. We then identify that the correlation between the data under protection and the EM leakage can be significantly reduced through data-dependent register reallocation and wire length adjustments. Simulation results on cryptographic circuits prove the effectiveness of both the constructed EM leakage model and the EM model-based CAD tool for EM side-channel security. [ABSTRACT FROM AUTHOR]

In East Asian countries including China, myopia has become a public hygiene issue that threatens the health of vast populations. In response to the huge market demand, a variety of products purportedly capable of treating myopia have been launched onto the market. Some manufacturers claim that juvenile myopia can be effectively controlled, or even cured, using their VR devices and software. Can VR devices be used for the prevention and control of juvenile myopia under existing technical conditions? In order to answer this question, the authors of this article analyzed the pathogenesis of myopia and the technical features of VR. [ABSTRACT FROM AUTHOR]

Logic encryption, as a hardware security technique, can protect integrated circuits (ICs) by inserting additional gates. The inserted gates guarantee that predefined outputs are only generated when correct key inputs are provided, preventing IC counterfeiting, intellectual property (IP) theft, and IC overproduction. To evaluate the logic encryption's robustness, two major criteria are usually utilized, which are (1) the interdependency between the keys and (2) the output corruption against attacks, including path sensitization attack, SATbased attack, hill-climbing attack, etc. However, the majority of existing logic encryption methods emphasize one criterion over the other. In this paper, an enhanced logic encryption method with a fully correlated key interdependency block is proposed. The method enhances the interdependency of keys and determines the locations of key-gates utilizing a rare node analysis method. Experimental results validate that the proposed method can withstand path sensitization attack and ensure 50% Hamming distance with reasonable design overheads. [ABSTRACT FROM AUTHOR]

Abstract: Septic cardiomyopathy (SCM) is a serious complication caused by sepsis that will further exacerbate the patient's prognosis. However, immune-related genes (IRGs) and their molecular mechanism during septic cardiomyopathy are largely unknown. Therefore, our study aims to explore the immune-related hub genes (IRHGs) and immune-related miRNA-mRNA pairs with potential biological regulation in SCM by means of bioinformatics analysis and experimental validation., Method: Firstly, screen differentially expressed mRNAs (DE-mRNAs) from the dataset GSE79962, and construct a PPI network of DE-mRNAs. Secondly, the hub genes of SCM were identified from the PPI network and the hub genes were overlapped with immune cell marker genes (ICMGs) to further obtain IRHGs in SCM. In addition, receiver operating characteristic (ROC) curve analysis was also performed in this process to determine the disease diagnostic capability of IRHGs. Finally, the crucial miRNA-IRHG regulatory network of IRHGs was predicted and constructed by bioinformatic methods. Real-time quantitative reverse transcription-PCR (qRT-PCR) and dataset GSE72380 were used to validate the expression of the key miRNA-IRHG axis., Result: The results of immune infiltration showed that neutrophils, Th17 cells, Tfh cells, and central memory cells in SCM had more infiltration than the control group; A total of 2 IRHGs were obtained by crossing the hub gene with the ICMGs, and the IRHGs were validated by dataset and qRT-PCR. Ultimately, we obtained the IRHG in SCM: THBS1. The ROC curve results of THBS1 showed that the area under the curve (AUC) was 0.909. Finally, the miR-222-3p/THBS1 axis regulatory network was constructed., Conclusion: In summary, we propose that THBS1 may be a key IRHG, and can serve as a biomarker for the diagnosis of SCM; in addition, the immune-related regulatory network miR-222-3p/THBS1 may be involved in the regulation of the pathogenesis of SCM and may serve as a promising candidate for SCM therapy., Competing Interests: The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest., (Copyright © 2022 Li, Sun, Ma, Wu, Li, Ding, Lu, Li, Yang, Li, Yang, Peng, Meng and Wang.)

Information system security has been in the spotlight of individuals and governments in recent years. Integrated Circuits (ICs) function as the basic element of communication and information spreading, therefore they have become an important target for attackers. From this perspective, system-level protection to keep chips from being attacked is of vital importance. This paper proposes a novel method based on a fringing electric field (FEF) sensor to detect whether chips are dismantled from a printed circuit board (PCB) as system-level protection. The proposed method overcomes the shortcomings of existing techniques that can be only used in specific fields. After detecting a chip being dismantled from PCB, some protective measures like deleting key data can be implemented to be against attacking. Fringing electric field sensors are analyzed through simulation. By optimizing sensor's patterns, areas and geometrical parameters, the methods that maximize sensitivity of fringing electric field sensors are put forward and illustrated. The simulation is also reproduced by an experiment to ensure that the method is feasible and reliable. The results of experiments are inspiring in that they prove that the sensor can work well for protection of chips and has the advantage of universal applicability, low cost and high reliability.