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6. Hot carrier degradation in deep submicron n-MOS technologies

7. Scaling behavior of ferroelectric FET with reduction in number of domains in ferroelectric layer.

8. Investigation of Gate-Length Scaling of Ferroelectric FET.

9. Mitigating Pillar-to-Pillar Variability of Ground Select Transistor in 3-D NAND Flash Memory.

10. Mitigating the Passing Word Line Induced Soft Errors in Saddle Fin DRAM.

11. Mitigating the Impact of Channel Tapering in Vertical Channel 3-D NAND.

12. Improvement of Row Hammering Using Metal Nanoparticles in DRAM—A Simulation Study.

13. Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory.

15. Signal Integrity Analysis in Carbon Nanotube Based Through-Silicon Via.

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