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The field of bioelectronics with the aim to contact cells, cell clusters, biological tissues and organoids has become a vast enterprise. Currently, it is mainly relying on classical micro‐ and nanofabrication methods to build devices and systems. Very recently the field is highly pushed by the development of novel printable organic, inorganic and biomaterials as well as advanced digital printing technologies such as laser and inkjet printing employed in this endeavor. Recent advantages in alternative additive manufacturing and 3D printing methods enable interesting new routes, in particular for applications requiring the incorporation of delicate biomaterials or creation of 3D scaffold structures that show a high potential for bioelectronics and building of hybrid bio‐/inorganic devices. Here the current state of printed 2D and 3D electronic structures and related lithography techniques for the interfacing of electronic devices with biological systems are reviewed. The focus lies on in vitro applications for interfacing single cell, cell clusters, and organoids. Challenges and future prospects are discussed for all‐printed hybrid bio/electronic systems targeting biomedical research, diagnostics, and health monitoring. [ABSTRACT FROM AUTHOR]

Printed electronics including large‐area sensing, wearables, and bioelectronic systems are often limited to simple circuits and hence it remains a major challenge to efficiently store data and perform computational tasks. Memristors can be considered as ideal candidates for both purposes. Herein, an inkjet‐printed memristor is demonstrated, which can serve as a digital information storage device, or as an artificial synapse for neuromorphic circuits. This is achieved by suitable manipulation of the ion species in the active layer of the device. For digital‐type memristor operation resistive switching is dominated by cation movement after an initial electroforming step. It allows the device to be utilized as non‐volatile digital memristor, which offers high endurance over 12 672 switching cycles and high uniformity at low operating voltages. To use the device as an electroforming‐free, interface‐based, analog‐type memristor, anion migration is exploited which leads to volatile resistive switching. An important figure of merits such as short‐term plasticity with close to biological synapse timescales is demonstrated, for facilitation (10–177 ms), augmentation (10s), and potentiation (35 s). Furthermore, the device is thoroughly studied regarding its metaplasticity for memory formation. Last but not least, the inkjet‐printed artificial synapse shows non‐linear signal integration and low‐frequency filtering capabilities, which renders it a good candidate for neuromorphic computing architectures, such as reservoir computing. [ABSTRACT FROM AUTHOR]

In this Letter, we report an inkjet-printed resistive switching device based on an Ag/ZnO/Au structure. The device exhibits bipolar resistive switching behavior, a low operation voltage of about 0.7 V, a high on/off ratio of 107, a long retention time exceeding 104 s, and good endurance. The conduction mechanism of the device in low and high resistive states was studied and showed good consistency with the theory of Ohmic and space charge limited conduction mechanisms, respectively. [ABSTRACT FROM AUTHOR]

Low-frequency noise is a critical characteristic of transistors, but there are only a few experimental works on the noise in printed electronics. In this work, we characterize the low-frequency noise of inkjet-printed electrolyte-gated thin-film transistors (EGTs) with indium-oxide semiconductors. We confirm that the carrier number fluctuation with correlated mobility fluctuation is the dominating noise generation mechanism. Also, we present the benchmark analysis on the noise level of various thin-film technologies. Notably, the extracted value of trap density near the insulator-channel interface is high, indicating an inferior quality of solution-processed and inkjet-printed thin-films. However, because of electrolyte-gating, the large areal gate capacitance compensates the negative effect of the high trap density, effectively reducing the flat-band voltage noise. As a result, the normalized drain current noise is considerably lower than solution-processed transistors and comparable with sputtered inorganic transistors with dielectric gating. This renders the electrolyte-gating approach useful in reducing the noise for printed/solution-based transistors, suitable for low-noise applications. [ABSTRACT FROM AUTHOR]

Unlike nanoscale silicon transistors, printed thin-film transistors usually rely on micrometer size channel lengths. The device dimensions, the morphology of the channel material, and the interface properties strongly influence important device parameters such as the threshold voltage (Vth) and the transconductance parameter (k). In this article, we analyze and model the dependence of critical electrical device properties of printed, electrolyte-gated transistors, based on crystalline indium oxide channel, for various device geometries. It is shown that the threshold voltage scales with the charge density at the electrolyte channel interface and is hence linearly dependent on the channel length (L). Furthermore, nonlinear scaling effects in the transconductance parameter and in the ON-current are studied, which turn out to be dependent on both, channel width and length. Finally, we present a scaling model capturing the width/length dependencies of the studied transistor technology which enables the correct simulation of logic gates. [ABSTRACT FROM AUTHOR]

Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures against RE, such as camouflaging. In this article, we propose a printed camouflaged logic cell that can be inserted into PE circuits to thwart RE. The proposed cell is based on three components achieved by changing the fabrication process that exploits the additive manufacturing feature of PE. These components are optically look-alike, while their electrical behaviors are different, functioning as a transistor, short, and open. The properties of the proposed cell and standard PE cells are compared in terms of voltage swing, delay, power consumption, and area. Moreover, the proposed camouflaged cell is fabricated and characterized to prove its functionality. Furthermore, numerous camouflaged components are fabricated, and their (in)distinguishability is assessed to validate their optical similarities based on the recent RE attacks on PE. The results show that the proposed cell is a promising candidate to be utilized in camouflaging PE circuits with negligible overhead. [ABSTRACT FROM AUTHOR]

In this report, we have studied field-effect transistors (FETs) using low-density alumina for electrolytic gating. Device layers have been prepared starting from the structured ITO glasses by printing the In2O3 channels, low-temperature atomic layer deposition (ALD) of alumina (Al2O3), and printing graphene top gates. The transistor performance could be deliberately changed by alternating the ambient humidity; furthermore, ID,ON/ID,OFF-ratios of up to seven orders of magnitude and threshold voltages between 0.66 and 0.43 V, decreasing with an increasing relative humidity between 40% and 90%, could be achieved. In contrast to the common usage of Al2O3 as the dielectric in the FETs, our devices show electrolyte-type gating behavior. This is a result from the formation of protons on the Al2O3 surfaces at higher humidities. Due to the very high local capacitances of the Helmholtz double layers at the channel surfaces, the operation voltage can be as low as 1 V. At low humidities (≤30%), the solid electrolyte dries out and the performance breaks down; however, it can fully reversibly be regained upon a humidity increase. Using ALD-derived alumina as solid electrolyte gating material, thus, allows low-voltage operation and provides a chemically stable gating material while maintaining low process temperatures. However, it has proven to be highly humidity-dependent in its performance. [ABSTRACT FROM AUTHOR]

Printed and flexible metal-oxide transistor technology has recently demonstrated great promise due to its high performance and robust mechanical stability. Herein, fully printed inverter structures using electrolyte-gated oxide transistors on a flexible polyimide (PI) substrate are discussed in detail. Conductive graphene ink is printed as the passive structures and interconnects. The additive printed transistors on PI substrates show an Ion=Ioff ratio of 106 and show mobilities similar to the state-of-the-art printed transistors on rigid substrates. Printed meander structures of graphene are used as pull-up resistances in a transistor-- resistor logic to create fully printed inverters. The printed and flexible inverters show a signal gain of 3.5 and a propagation delay of 30 ms. These printed inverters are able to withstand a tensile strain of 1.5% following more than 200 cycles of mechanical bending. The stability of the electrical direct current (DC) properties has been observed over a period of 5 weeks. These oxide transistor-based fully printed inverters are relevant for digital printing methods which could be implemented into roll-to-roll processes. [ABSTRACT FROM AUTHOR]

Electrolyte-gated thin-film transistors (EGTs) with indium oxide channel, and expected lifetime of three months, enable low-voltage operation (~1 V) in the field of printed electronics (PEs). The channel width of our printed EGTs is varied between 200 and 1000 μm, whereas a channel length between 10 and 100 μm is used. Due to the lack of uniform performance p-type metal oxide semiconductors, n-type EGTs and passive elements are used to design circuits. For logic gates, transistor–resistor logic has been employed so far, but depletion- and enhancement-mode EGTs in a transistor–transistor logic boost the circuit performance in terms of delay and signal swing. In this article, the threshold voltage of the EGT, which determines the operation mode, is tuned through sizing of the EGTs channel geometry. The feasibility of both transistor operation modes is demonstrated for logic gates and ring oscillators. An inverter operating at a supply voltage of 1 V shows a maximum gain of 9.6 and a propagation delay time of 0.7 ms, which represents an improvement of ~2 × for the gain and oscillation frequency, in comparison with the resistor–transistor logic design. Moreover, the power consumption is reduced by 6 ×. [ABSTRACT FROM AUTHOR]

Printed electronics can benefit from the deployment of electrolytes as gate insulators, which enables a high gate capacitance per unit area (1– 10 μF cm−2) due to the formation of electrical double layers (EDLs). Consequently, electrolyte-gated field-effect transistors (EGFETs) attain high-charge carrier densities already in the subvoltage regime, allowing for low-voltage operation of circuits and systems. This article presents a systematic study of lumped terminal capacitances of printed electrolyte-gated transistors under various dc bias conditions. We perform voltage-dependent impedance measurements and separate extrinsic components from the lumped terminal capacitance. The proposed Meyer-like capacitance model, which also accounts for the nonquasi-static (NQS) effect, agrees well with experimental data. Finally, to verify the model, we implement it in Verilog-A and simulate the transient response of an inverter and a ring oscillator circuit. Simulation results are in good agreement with the measurement data of fabricated devices. [ABSTRACT FROM AUTHOR]

Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation. [ABSTRACT FROM AUTHOR]

Printed electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication and the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things. To use printed batteries or printed energy harvesters in the future, electrolyte-gated field-effect transistors (EGFETs) based on inorganic materials enable printed circuits requiring small supply voltage and low power. Since these applications need secure communication and/or authentication, it is imperative to embed security primitives for cryptographic key and identification purposes into the applications. Physical unclonable functions (PUFs) have been adopted widely to provide secure keys. In this paper, we present the design, simulation, fabrication, and measurements of a PUF based on EGFETs using inorganic inkjet PE. A comprehensive framework, including Monte Carlo simulations calibrated on real device measurements, is developed. Moreover, a multibit PE-PUF design is proposed to optimize area usage. Our simulation results show that the PE-PUF has ideal uniqueness (50.1%) and good reliability (89%). In addition, the proposed multibit PE-PUF reduces the area usage around 30%. The proposed PE-PUF was fabricated and the experimental results confirm that the PE-PUF can operate reliably as low as 0.5 V, and hence, it is a remarkable candidate to be utilized in low-power applications. [ABSTRACT FROM AUTHOR]

A printed electronics technology has the advantage of additive and extremely low-cost fabrication compared with the conventional silicon technology. Specifically, printed electrolyte-gated field-effect transistors (EGFETs) are attractive for low-cost applications in the Internet-of-Thingsdomain as they can operate at lowsupply voltages. In this paper, we propose an empirical dc model for EGFETs,which can describe the behavior of the EGFETs smoothly and accurately over all regimes. The proposed model, built by extending the Enz--Krummenacher--Vittoz model, can also be used to model process variations,which was not possible previously due to fixed parameters for near threshold regime. It offers a single model for all the operating regions of the transistors with only one equation for the drain current. Additionally, it models the transistors with a less number of parameters but higher accuracy compared with existing techniques. Measurement results from several fabricated EGFETs confirm that the proposed model can predict the I-V more accurately compared with the state-of-the-art models in all operating regions. Additionally, the measurements on the frequency of a fabricated ring oscillator are only 4.7% different from the simulation results based on the proposed model using values for the switching capacitances extracted from measurement data, which showsmore than 2x improvement comparedwith the state-of-the-art model. [ABSTRACT FROM AUTHOR]

Printed electronic components offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, to be compatible to the fields of smart sensors, Internet of Things, and wearables, it is essential that devices operate at small supply voltages. In printed electronics, mostly silicon dioxide or organic dielectrics with low dielectric constants have been used as gate isolators, which in turn have resulted in high power transistors operable only at tens of volts. Here, we present inkjet printed circuits which are able to operate at supply voltages as low as ~2V. Our transistor technology is based on lithographically patterned drive electrodes, the dimensions of which are carefully kept well within the printing resolutions; the oxide semiconductor, the electrolytic insulator and the top-gate electrodes have been inkjet printed. Our inverters show a gain of ~4 and 2.3 ms propagation delay time at 1V supply voltage. Subsequently built 3-stage ring oscillators start to oscillate at a supply voltage of only 0.6V with a frequency of ~255 Hz and can reach frequencies up to ~350 Hz at 2V supply voltage. Furthermore, we have introduced a systematic methodology for characterizing ring oscillators in the printed electronics domain, which has been largely missing. Benefiting from this procedure, we are now able to predict the switching capacitance and driver capability at each stage, as well as the power consumption of our inkjet printed ring oscillators. These achievements will be essential for analyzing the performance and power characteristics of future inkjet printed digital circuits. [ABSTRACT FROM AUTHOR]

High mobility, electrolyte-gated FETs (EGFETs), based on precursor-derived oxide semiconductors, enable the possibility of achieving printed and low voltage (<2 V) operated circuits. These EGFETs can also be realized with displaced-gate geometries. However, the displaced-gate devices are typically slow due to high electrolyte resistance resulting from the large gate–channel distances. Here, we show that a thin insulating (composite solid polymer electrolyte) layer and a top-gate geometry can largely overcome this limitation, a comprehensive comparison between the displaced-gate and the top-gate devices has been provided. In order to facilitate circuit design, we have successfully developed accurate models to predict the behavior of these top-gate EGFETs. The importance of our modeling approach is further enhanced by the fact that appropriate predictive modeling strategies for printed circuits, especially for those that are based on oxide semiconductors, are largely missing. Unlike existing transistor models that do not cover all voltage regimes (below, near, and above threshold), we propose a new modeling methodology that matches very well with the measured data, is continuous and smooth over the entire voltage range, and can be easily incorporated into SPICE simulators. [ABSTRACT FROM PUBLISHER]

Keywords: electrolyte-gated transistors; ink-jet print; ion-gels; ionic liquids; printed electronics The self-assembling ion-gel can be ink-jet printed and therefore enables printing of chemically crosslinked ion-gels. Electrolyte-gated transistors, ink-jet print, ion-gels, ionic liquids, printed electronics. [Extracted from the article]

Electrolyte‐gated transistors (EGTs) represent an interesting alternative to conventional dielectric‐gating to reduce the required high supply voltage for printed electronic applications. Here, a type of ink‐jet printable ion‐gel is introduced and optimized to fabricate a chemically crosslinked ion‐gel by self‐assembled gelation, without additional crosslinking processes, e.g., UV‐curing. For the self‐assembled gelation, poly(vinyl alcohol) and poly(ethylene‐alt‐maleic anhydride) are used as the polymer backbone and chemical crosslinker, respectively, and 1‐ethyl‐3‐methylimidazolium trifluoromethanesulfonate ([EMIM][OTf]) is utilized as an ionic species to ensure ionic conductivity. The as‐synthesized ion‐gel exhibits an ionic conductivity of ≈5 mS cm−1 and an effective capacitance of 5.4 µF cm−2 at 1 Hz. The ion‐gel is successfully employed in EGTs with an indium oxide (In2O3) channel, which shows on/off‐ratios of up to 1.3 × 106 and a subthreshold swing of 80.62 mV dec−1. [ABSTRACT FROM AUTHOR]

Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV-visible light and UV-laser), we demonstrate facile fabrication of high performance In 2 O 3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.