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This article presents a technique to suppress noise in switched-capacitor (SC) radio frequency (RF) receivers (RXs). In the proposed technique, the sampling capacitor of a typical SC-RX is realized using a MOS capacitor. Furthermore, the same sampling MOS capacitor is switched between the inversion and depletion regions to act as a discrete-time parametric amplifier for downconverted signals. Due to the voltage gain at the front end, the noise of successive stages in the receiver chain is suppressed. Analytical expressions for the conversion gain, input impedance, and noise figure (NF) of the gain-boosted SC receiver are derived and verified through simulations. A prototype SC receiver is implemented in a CMOS 180-nm technology. In measurements, the receiver achieved 41-dB conversion gain and 3.1-dB NF over the tuning range of 0.2-to-0.95 GHz. The reduction in NF due to the parametric gain boost is >10 dB. [ABSTRACT FROM AUTHOR]

An RF-choke (RFC) is a crucial but difficult-to-realize component of all Class-E power amplifiers (PAs). A Class-DE PA does not require an RFC but requires two non-overlapping clocks for its operation. This brief presents an RFC-less Class-E PA which operates with a single 50% duty-cycled clock. Analytical expressions for the switch voltages and currents in the proposed PA are derived and validated. Design equations are provided. A prototype RFC-less Class-E PA is implemented in CMOS 180 nm technology. Measurements show that the PA can deliver +21.5 dBm peak output power at 1 GHz with a system efficiency of 41.1%. The measured second and third harmonic distortions at the peak power are −46 dBc and −48.47 dBc, respectively. [ABSTRACT FROM AUTHOR]

Input-match, noise figure (NF), in-band (IB) third-order input-referred intercept point (IIP3), out-of-band (OB) IIP3, and power consumption are five crucial performance metrics of a radio frequency (RF) receiver. In a typical passive mixer-first receiver, these five performance metrics are tightly coupled with each other. In this article, a second-order baseband noise-canceling (NC) scheme is proposed to break the performance tradeoffs in an N-path mixer-first receiver. Analytical expressions for input impedance, NF, IB-IIP3, and OB-IIP3 of the proposed NC receiver are derived and verified. A prototype mixer-first receiver is implemented in CMOS 180 nm technology and tested in the laboratory. In measurements, the receiver achieves an NF less than 4 dB and IB-IIP3 of +14.5 dBm over a frequency range of 0.2–1.2 GHz. The measured OB-IIP3 is +25 dBm at a frequency offset of 2.2 times the bandwidth while consuming a static power of 20 mW. [ABSTRACT FROM AUTHOR]

This paper presents a frequency-agile in-band full-duplex (FD) receiver based on a switched-capacitor continuous-mode vector modulator (VM). The passive VM presented in this paper provides simultaneous downmixing, attenuation, and phase shifting and is used to generate a baseband canceler signal for self-interference (SI) cancelation. A prototype FD receiver is implemented in CMOS 130 nm technology. The receiver is tunable from 0.1 to 0.95 GHz. In FD mode at 900 MHz, the receiver has an effective input-referred third-order intercept power (IIP3) of +7 dBm, SI-to-noise-and-distortion-ratio (SINDR) of ≈ +65.3 dB at −27.5 dBm SI in 15 MHz bandwidth, and noise figure (NF) degradation of less than 1 dB. [ABSTRACT FROM AUTHOR]

Dual port, aperture coupled and tapered fed patch antenna with high isolation is proposed for full‐duplex 2.4 GHz ISM applications. This antenna can achieve a measured isolation of around 60 dB at 2.4 GHz and isolation band of 2.3‐2.6 GHz for more than 59.5 dB. Such a high isolation surpasses the isolation performance of dual‐port antennas available in the literature. [ABSTRACT FROM AUTHOR]

Inductorless wide-band low-noise amplifiers (LNAs) usually suffer from poor noise performance, mainly due to the high noise contribution of the matching device. Noise canceling (NC) is a technique used in wide-band LNAs [1]-[13] to nullify the noise contribution of the matching device at the output. NC techniques are often explained with the help of the block diagram shown in Figure 1(a), where the input signal from a source of internal impedance Rs is simultaneously fed to a matching amplifier and a voltage sensing amplifier. [ABSTRACT FROM PUBLISHER]