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Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. This article describes, for the first time, the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10-GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the tradeoff in flexibility, speed, and area. The design, which is taped out in a 180-nm high-voltage CMOS process, utilizes buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock speed of high-voltage silicon integrated circuits and a fully digital architecture to provide robustness under high slew rates of the ground rail. The driver IC has networks of 100-ps delay elements that are configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering, and pulse generation. The driver IC is experimentally evaluated to have a 100-ps resolution and to operate reliably in a 400-V gallium nitride (GaN) bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.

A strong candidate device for use in high-efficiency and high-density power converters is the SiC bipolar junction transistor, which requires a continuous gate (base) current to maintain its on -state. A base driver circuit with regenerative collector current feedback using a current transformer, and a negative off -state base-emitter voltage is presented in this article. The off -state base-emitter voltage required to prevent simultaneous conduction of a commercially available device when subjected to d v /d t’ s is assessed. The device is then utilized in a three-phase dc-to-ac power converter where the efficacy of using the proposed base driver is evaluated. The off -state base-emitter voltage used is informed by the d v /d t tests. The converter is supplied from a 600-V dc rail, switches at 50 kHz and supplies a 4.1-kW load at a modulation index of 0.9. An efficiency of 97.4% was measured.

Widespread adoption of electric vehicles will require ac power distribution systems to accommodate high penetrations of power electronic loads, placing increasing demands on the power quality of grid-connected converters. Recent developments in devices and circuit topologies have the potential to improve the intrinsic power quality of these grid interface inverters, reducing the need for passive filters and associated reactive power consumption. Wide bandgap devices, such as SiC, have recently gained much attention due to their low switching losses facilitating raised pulsewidth modulation frequencies. However, the high cost of SiC together with electromagnetic interference (EMI) resulting from very rapid switching transitions necessary to realize low switching losses cause concern. Previous research in Si MOSFET modular multilevel converters (MMC) suggests a high-efficiency alternative with potential for lower EMI. Si MOSFET MMC benefits are enhanced with parallel-connected devices and slowed switching, made possible by low effective switching frequency. This paper uses experimental results to explore the impact of parallel connection and slowed switching on Si MOSFET MMC losses, and presents improved Si MOSFET switching loss models to resolve inaccuracies observed with conventional Si MOSFET models. EMI is then compared between SiC and Si MMC using carefully controlled relative measurements of radiated EMI.

A highly efficient 5-kW bidirectional dc–dc converter power stage operating from a 400-V supply implementing super-junction (SJ) metal–oxide–semiconductor field-effect transistor (MOSFETs) is presented. SJ MOSFETs have low on-state resistances and low switching losses. However, their application in voltage-source converters can be compromised by the reverse recovery behavior of their intrinsic diodes and their highly nonlinear output capacitances. A series switching-aid circuit is used to control the output capacitance charging current. The dead times between switching transitions are assessed and optimized in order to deactivate the intrinsic diodes. The combination of these techniques enables very high efficiencies to be attained. Calorimetric measurements indicate a full-load efficiency of 99.1% for the prototype 5-kW dc–dc converter power stage. A loss reduction of approximately 50% is achieved with the prototype converter power stage when compared to an equivalent insulated-gate bipolar transistor (IGBT)-based power stage. Lastly, a loss versus duty cycle function is experimentally determined, which can be used to inform the design of a maximum efficiency point tracking system.

An SMPS for hybrid electric vehicle and electric vehicle applications is presented. The use of SiC BJTs in the primary-side switching circuitry is investigated. Practical deployment aspects are addressed. Particular attention is given to the design of the BJT base driver stage and a bespoke turn-on switching-aid circuit. Mathematical design calculations are not presented, but the proposed circuitry is demonstrated in a 1-kW isolated-output DC-DC converter operating from 800 V and supplying 48 V at a switching frequency of 60 kHz. Full-load efficiency was evaluated at 93.3% using a calorimeter.

Active gate driving provides an opportunity to reduce EMI in power electronic circuits. Whilst it has been demonstrated for MOS-gated silicon power semiconductor devices, reported advanced gate driving in wide-bandgap devices has been limited to a single impedance change during the device switching transitions. For the first time, this paper shows multi-point gate signal profiling at the sub-ns resolution required for GaN devices. A high-speed, programmable active gate driver is implemented with an integrated high-speed memory and output stage to realise arbitrary gate pull-up and pulldown resistance profiles. The nominal resistance range is 120 μΩ to 64 Ω, and the timing resolution of impedance changes is 150 ps. This driver is used in a 1 MHz GaN bridge leg that represents a synchronous buck converter. It is demonstrated that the gate voltage profile can be manipulated aggressively in nanosecond scale. It is observed that by profiling the first 5 ns of the control device's gate voltage transient, a reduction in switch-node voltage oscillations is observed, resulting in an 8–16 dB reduction in spectral power between 400 MHz and 1.8 GHz. This occurs without an increase in switching loss. A small increase in spectral power is seen below 320 MHz. As a baseline for comparison, the GaN bridge leg is operated with a fixed gate drive strength. It is concluded that p-type gate GaN HFETs are actively controllable, and that EMI can be reduced without increasing switching loss.

The paper assesses the potential of employing super-junction MOSFETs in a high efficiency and low cost bidirectional DCDC converter for application in electric vehicle systems. Super-junction MOSFETs have a very low conduction loss, however, their poor intrinsic diode recovery behaviour and high output capacitances means that switching losses can be high in voltage source converters. A drain current injection technique is presented that can be used to mitigate the poor switching characteristics and thus realise excellent power conversion efficiencies. Experimental results are given for a circuit operating at 400V, 5kW and 25kHz and the means of achieving a power conversion efficiency >99% is outlined.

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd/dt slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.

This paper presents a high efficiency 5-kW bidirectional DC-DC converter for use in electric vehicle super-capacitor systems. Super-junction MOSFETs are deployed in the power stage to minimize losses. This is achieved using a snubber inductor and by arranging the gate signal underlap delays in order to control charging current caused by the devices' highly non-linear output capacitance and to deactivate the intrinsic body drain diode respectively. The result is a 5-kW power converter with an estimated efficiency exceeding 99% in the power semiconductor stage and requiring no forced cooling.

Silicon super-junction MOSFETs have very low on-state resistances and fast switching characteristics. However, their use in voltage-source converters is hindered by the poor reverse recovery performance of their body drain diode and an adverse output capacitance characteristic. These both act to increase the overall switching loss. The on-state resistance and output capacitance characteristics of super junction devices are both related to the area of the silicon die. As this increases, the on-state resistance decreases but the output capacitance increases. A figure of merit is evaluated with both predicted and experimental results using a 400-V, DC-DC synchronous buck-converter operating over a range of output currents and switching frequencies.

Power maximisation techniques in wideband vibration energy harvesting typically require the periodic sensing of input power or excitation frequency. This paper presents low- power circuits and sensing methods to obtain this information. First, an excitation frequency measurement circuit is presented that permits a reduced timer run-time compared to reported methods. Second, a power sensing method is presented, which extends the measurement range of reported techniques by adapting to the levels of the available power. Experimental results for the frequency measurement circuit tested in the range 35-51 Hz show a power consumption of 3.7 μW. The power-sensing technique is experimentally validated over a power range of 370690 μW, and its power consumption is 7.5 μW.