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Mechanical jerk systems have applications in several areas, such as oscillators, microcontrollers, circuits, memristors, encryption, etc. This research manuscript reports a new 3-D chaotic jerk system with two unstable balance points. It is shown that the proposed mechanical jerk system exhibits multistability with coexisting chaotic attractors for the same set of system constants but for different initial states. A bifurcation analysis of the proposed mechanical jerk system is presented to highlight the special properties of the system with respect to the variation of system constants. A field-programmable gate array (FPGA) implementation of the proposed mechanical jerk system is given by synthesizing the discrete equations that are obtained by applying one-step numerical methods. The hardware resources are reduced by performing pipeline operations, and, finally, the paper concludes that the experimental results of the proposed mechanical jerk system using FPGA-based design show good agreement with the MATLAB simulations of the same system. [ABSTRACT FROM AUTHOR]

It is well known that multiplication inside a computer does not follow the associative property because of roundoff effects. It is possible to use this fact to generate other different chaotic instances of chaotic maps or oscillators when a multiplication of three terms appears. Chaos is very sensitive to small changes in the initial conditions and amplifies these small rounding effects. We use this condition to build different chaotic instances, which give different results, of the Lü oscillator and the 2D map, and we show one application to create new instances of a pseudo random number generator using the 2D map. Both chaotic systems are simulated in software and in hardware within an FPGA where another 144 different 2D map instances and 81 different Lü oscillators can be created. To best of our knowledge, it is the first paper that analyze the construction of new chaotic entities by using the roundoff effects. [ABSTRACT FROM AUTHOR]

Applications relying on the Ethernet IEEE 802.3ba and IEEE802.3b standards require secure data encryption and authentication at extremely high speeds (at least 100 Gbit/s). The Galois/Counter Mode (GCM) is currently considered the de facto standard for hardware high-speed authenticated encryption, although other algorithms have been proposed in the literature such as the Offset Codebook Mode (OCB). The challenge in terms of providing security for high-speed applications is to achieve implementations that explore the parallelism of these algorithms; however, this translates into area cost. In this work, we propose an alternative to GCM and OCB. We show that a combination of the Offset Two-Round authenticated-encryption scheme with the AES block cipher (known as AES-OTR) is exceptionally well suited for exploiting fine-grained parallelism, and can therefore be used to achieve ultra-high-speed data encryption rates. The experiments reported in this paper show that our pipeline-parallel implementation of AES-OTR outperforms the GCM and OCB schemes in terms of throughput per area while using almost half of the logic resources. Our implementation used a Stratix 4 FPGA device as well as several devices from the Virtex family. Implementations of AES-OTR on Stratix 4 used 11kALMs and achieved a throughput of 143.65 Gbit/s. On the Virtex Ultrascale, our design used 31,859 LUTs with a throughput of 204.92 Gbit/s. [ABSTRACT FROM AUTHOR]

For almost one decade, the academic community has been working in the design and analysis of new lightweight primitives. This cryptography development aims to provide solutions tailored for resource-constrained devices. The U.S. National Institute of Standards and Technology (NIST) started an open process to create a Lightweight Cryptography Standardization portfolio. As a part of the process, the candidates must demonstrate their suitability for hardware implementation. Cost and performance are two of the criteria to be evaluated. In this work, we present the analysis of costs and performance in hardware implementations over five NIST LWC Round 2 candidates, COMET, ESTATE-AES/Gift, LOCUS, LOTUS, and Oribatida. Each candidate's implementation was adapted to the Hardware API for Lightweight Cryptography for fair benchmarking of hardware cores. The results were generated for Xilinx Artix-7 xc7a12tcsg325-3. The results indicate that it is feasible to achieve the reduction of each solution below 2000 LUTs and 2000 slices where some of them (the variants of ESTATE-AES/Gift) are below 850 LUTs and 600 FF when they are included in the LWC CryptoCore. [ABSTRACT FROM AUTHOR]