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Precise detection of obstacles is needed for the successful navigation of autonomous vessels. Recent approaches use semantic segmentation to better generalize to unknown scenarios. However, the majority do not consider computational complexity and constraints, which makes proposed architectures undeployable on edge VPUs. In this thesis, we develop a novel architecture based on state-of-the-art water segmentation and refinement network WaSR. We explore various encoders and decoder modifications to propose a novel architecture. Based on WaSR, TopFormer, designed for mobile semantic segmentation, and an abstracted transformer architecture MetaFormer, for which we propose previously unused token mixers, we introduce WaSRFormer. It uses a TopFormer-like decoder with MetaFormers for speedup and good practices from WaSR to deal with diverse water features. On challenging MODS benchmark, WaSRFormer achieves 92.98% and 86.27% F1 score overall and inside the danger zone, respectively, with only 0.51% and 0.25% drop in F1 score compared to WaSR. On a modern laptop GPU it runs more than 10x faster (115.45 FPS) than WaSR (10.94 FPS). To emphasize the practical contribution, we deploy WaSRFormer on the embedded low-power hardware OAK-D. While WaSR cannot even fit into this hardware, WaSRFormer comfortably runs at 5.45 FPS. Natačna detekcija ovir je pomembna za uspešno navigacijo avtonomnih plovil. Nedavna dela uporabljajo semantično segmentacijo za boljšo generalizacijo na še ne videnih primerih. Vendar večina predlaganih metod ne upošteva računskih zahtevnosti in omejitev, zaradi česar je modele nemogoče pognati na robnih napravah z vgrajenim VPU. V tem delu razvijemo novo arhitekturo osnovano na najsodobnješi arhitekturi za segmentacijo vodnih ovir, WaSR, in dodatno raziščemo številne kodirnike in modifikacije dekodirnikov. Na podlagi WaSR, TopFormerja, narejenega za hitro semantično segmentacijo, in abstrakcije transformerjev MetaFormerja, za katerega predlagamo še neuporabljene mešalnike žetonov, predstavimo WaSRFormer. Le-ta uporablja dekodirnik osnovan na TopFormerju, v katerega za pospešitev vgradimo MetaFormerje, dodatno pa uporabimo dobre prakse iz WaSR za obdelovanje raznolikih značilk vode. Na zahtevni množici MODS, WaSRFormer doseže 92.98% in 86.27% F1 gledano v celoti in znotraj nevarnega območja. V primerjavi z WaSR je to le 0.51% in 0.25% slabši F1. Na modernem GPU je WaSRFormer več kot 10x hitrejši (115.45 FPS) kot WaSR (10.94 FPS). Da poudarimo praktični prispevek, WaSRFormer poženemo na robni napravi OAK-D z nizko porabo energije. Medtem ko WaSR sploh ni mogoče pognati, WaSRFormer doseže 5.45 FPS.

International audience; Stereo matching techniques aim at reconstructing disparity maps from a pair of images. The use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algorithms. Local stereo matching algorithms are efficiently implemented on GPU and DSP. This paper presents the optimization of the One Dimension Belief Propagation (BP-1D) algorithm. BP-1D is faster than previous algorithms on monocore DSP and its implementation onto multicore DSPs is straightforward. BP-1D implemented on multicore embedded platforms out-performs previous stereo matching implementations reaching real-time performances for resolutions up to 1080p with a 10 Watts power consumption. © 2016 IEEE.

In this study, we present an integrated method for detecting and forecasting the health of gas turbine components as degraded over time. An advanced model-based real time performance adaptation approach is developed for detecting the degradation of engine components via a dynamic engine model that is built in Simulink. The detected health parameters of the engine component are then implemented in a discrete window-based analysis by a regression method in order to forecast their evolution. The proposed approach is tested for an engine with increased flexibility that characterizes modern gas turbine operations. The results demonstrate the promising capabilities of our advanced proposed method for accurate and efficient detection and forecast of the health of gas turbine compressors as degraded over time. 2016 IEEE. Qatar National Research Fund Scopus

Conference of 2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 ; Conference Date: 26 September 2013 Through 28 September 2013; Conference Code:102029; International audience; In many core architectures, clusters with shared memory banks offer a simple and efficient way (high throughput, low latency) to share and communicate data between close cores. Several recent embedded architectures are using such a design e.g. the MPPA chip from Kalray. Nonetheless, especially in the embedded world, as power consumption is an important preoccupation, shared memory is implemented as a set of single-port memory banks managed by a dedicated controller. As a consequence, some serialization is mandatory for concurrent accesses to banks. This means that memory access-time delays can occur on a regular basis, as each cluster is a multicore system by itself. This paper evaluates on a theoretical basis what kind of tradeoff is made by using such a design with regards to memory access-times and real-time performance: it evaluates the mean access-time with the default configuration of the MPPA chip on a probabilistic formalism, and gives a simplified expression of it. It also gives some typical values for use cases, and discuss the relevance of this design and its limitations with regards to the use of dataflow (CSDF) models of computation.

The contribution of this paper is to produce national smoothed growth indicators that describe the behaviour of economic activity at a monthly frequency, while utilizing a wide range of economic time series. New Eurocoin indicator, that is published monthly by the Bank of Italy, provides a summary index of the medium to long-run component (MLRG) of the gross domestic product (GDP) growth rate and only for the entire aggregate Euro area, by using the Generalized Dynamic Factor Model. The innovation of this research are some procedures, based on Eurocoin approach, to estimate MLRG in countries belonging to Euro Area. R

International audience; This paper deals with the design of a generic visual tracking algorithm suitable for a large class of camera (single viewpoint sensors). It is based on the estimation of the relationship between observations and motion on the sphere. This is efficiently achieved using a kernel-based regression function on a generic linearly-weighted sum of non-linear basis functions. We also present two set of experiments. The first one shows the efficiency of our algorithm through the tracking in video sequences acquired with three types of cameras (conventional, dioptric-fisheye and catadioptric). The real-time performances will be shown by tracking one or several planes. The second set of experiments presents an application of our tracking algorithm to visual servoing with a fisheye camera.

New Eurocoin (NE) is a synthetic and up-to-date statistics measure of the Euro-Area conjuncture. The target of NE is the medium to long-run component of the Euro Area GDP growth, that is published monthly by the Bank of Italy and CEPR. Estimations of NE are obtained through the generalized dynamic factor model. It is a well-known result in the literature isolating the business cycle in integrated series that band-pass filter could deteriorate at the end of the sample, being less reliable for the most recent data. This is very relevant for economic policy. Altissimo, Cristadoro, Forni, Lippi, Veronese (2008) develop, through New Eurocoin Indicator, a method to obtain smoothing of a stationary time series so as to avoid the occurrence of end-of-sample deterioration and short-run fluctuations. Since New Eurocoin indicator provides a summary index of the medium to long-run component (MLRG) of the GDP solely for the whole Euro area aggregate, the main contribution of this research is to propose some procedures to estimate the following disaggregated components of European GDP: - Sectoral smoothed growths; - MLRG concerning some countries belonging to the Euro Area; - Expenditure components.

Many image processing applications need real time performance, while having restrictions of size, weight and power consumption. These include a wide range of embedded systems from remote sensing applications to mobile phones. FPGA-based solutions are common for these applications, their main drawback being long development time. In this work a co-design methodology for processor-centric embedded systems with hardware acceleration using FPGAs is applied to an image processing method for localization of multiple robots. The goal of the methodology is to achieve a real-time embedded solution using hardware acceleration, but with development time similar to software projects. The final embedded co-designed solution processes 1600×1200 pixel images at a rate of 25 fps, achieving a 12.6× acceleration from the original software solution. This solution runs with a comparable speed as up-to-date PC-based systems, and it is smaller, cheaper and demands less power. © 2012 Springer-Verlag. Fil:Pedre, S. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina.

Recently a new recipe for developing and deploying real-time systems has become increasingly adopted in the JET tokamak. Powered by the advent of x86 multi-core technology and the reliability of the JET’s well established Real-Time Data Network (RTDN) to handle all real-time I/O, an official Linux vanilla kernel has been demonstrated to be able to provide realtime performance to user-space applications that are required to meet stringent timing constraints. In particular, a careful rearrangement of the Interrupt ReQuests’ (IRQs) affinities together with the kernel’s CPU isolation mechanism allows to obtain either soft or hard real-time behavior depending on the synchronization mechanism adopted. Finally, the Multithreaded Application Real-Time executor (MARTe) framework is used for building applications particularly optimised for exploring multicore architectures. In the past year, four new systems based on this philosophy have been installed and are now part of the JET’s routine operation. The focus of the present work is on the configuration and interconnection of the ingredients that enable these new systems’ real-time capability and on the impact that JET’s distributed real-time architecture has on system engineering requirements, such as algorithm testing and plant commissioning. Details are given about the common real-time configuration and development path of these systems, followed by a brief description of each system together with results regarding their real-time performance. A cycle time jitter analysis of a user-space MARTe based application synchronising over a network is also presented. The goal is to compare its deterministic performance while running on a vanilla and on a Messaging Real time Grid (MRG) Linux kernel.

International audience; We provide a general tool to improve the real time performance of a broad class of Union-Find algorithms. This is done by minimizing the random access memory that is used and thus to avoid the well-known von Neumann bottleneck of synchronizing CPU and memory. A main application to image segmentation algorithms is demonstrated where the real time performance is drastically improved.