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In this work, a ten-level inverter scheme is presented to extend the linear modulation range (LMR) by using a unique space vector pulsewidth modulation (SVPWM) technique, such that no lower order harmonics (such as 5th, 7th, 11th, and 13th, etc.) are present in the phase voltage as compared to six-step mode operation. The proposed scheme can increase the peak phase fundamental voltage of the inverter from 0.577 to $0.637 V_{dc}$ (maximum possible peak phase fundamental voltage of a conventional hexagonal space vector structure (SVS) voltage source inverters while operating in six-step mode), irrespective of the load power factor (p.f), where $V_{dc}$ is the dc link voltage of the inverter. The ten-level inverter structure is formed using a two-level inverter and an H-bridge (HB) in cascade from one end and a floating capacitor-based two-level inverter cascaded with an HB from the other end to drive an open-end winding induction motor (OEWIM). All the HB capacitor voltages are balanced by using space vector redundancy. The claim of balancing the capacitor voltages throughout the whole modulation range is verified experimentally in this article. Experimental results at different steady-state and transient conditions are shown to validate the proposed inverter scheme’s efficacy in increasing the LMR. [ABSTRACT FROM AUTHOR]

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/f” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented. [ABSTRACT FROM AUTHOR]

This article proposes a method of generating 24-sided polygonal voltage space vector structure composed of 24 real active vectors and a zero vector. Each active vector is a real vector in contrast to switched average vectors in literature. Generation of real 24-sided vectors minimizes switching losses and improves quality of phase voltage compared to switched averaged vectors technique. An important feature of the presented scheme is elimination of lower order harmonics up to 19th order from motor phase voltage throughout the modulation range that gives reduction in torque pulsation and near sinusoidal phase current. The proposed scheme extends the linear modulation range till 99.42 $\%$. Open-end winding induction motor is fed with primary and secondary inverters from either ends. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both the inverters are realized using a simple star-delta transformer combination. The proposed concepts are verified with laboratory prototype and the respective results during the steady-state, transient, and fault scenario are presented. The supporting loss analysis and harmonic performance of the proposed drive is performed with existing topologies. [ABSTRACT FROM AUTHOR]