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The role of resting frontal alpha-asymmetry in explaining neural-mechanisms of affect and approach/withdrawal behavior is still debatable. The present study explores the ability of the quasi-stable resting EEG asymmetry information and the associated neurovascular synchronization/desynchronization in bringing more insight into the understanding of neural-mechanisms of affect and approach/withdrawal behavior. For this purpose, a novel frontal alpha-asymmetry based on microstates, that assess quasi-stable EEG scalp topography information, is proposed and compared against standard frontal-asymmetry. Both proposed and standard frontal alpha-asymmetries were estimated from thirty-nine healthy volunteers resting-EEG simultaneously acquired with resting-fMRI. Further, neurovascular mechanisms of these asymmetry measures were estimated through EEG-informed fMRI. Subsequently, the Hemodynamic Lateralization Index (HLI) of the neural-underpinnings of both asymmetry measures was assessed. Finally, the robust correlation of both asymmetry-measures and their HLI’s with PANAS, BIS/BAS was carried out. The standard resting frontal-asymmetry and its HLI yielded no significant correlation with any psychological-measures. However, the microstate resting frontal-asymmetry correlated significantly with negative affect and its neural underpinning’s HLI significantly correlated with Positive/Negative affect and BIS/BAS measures. Finally, alpha-BOLD desynchronization was observed in neural-underpinning whose HLI correlated significantly with negative affect and BIS. Hence, the proposed resting microstate-frontal asymmetry better assesses the neural-mechanisms of affect, approach/withdrawal behavior.

In this paper, for the first time, a two-dimensional (2D) analytical drain current model for sub-100 nm multi-layered gate material engineered trapezoidal recessed channel (MLGMETRC) MOSFET: a novel design is presented and investigated using ATLAS and DEVEDIT device simulators, to mitigate the large gate leakages and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The twodimensional (2D) analytical model based on solution of Poisson-s equation in cylindrical coordinates, utilizing the cylindrical approximation, has been developed which evaluate the surface potential, electric field, drain current, switching metric: ION/IOFF ratio and transconductance for the proposed design. A good agreement between the model predictions and device simulation results is obtained, verifying the accuracy of the proposed analytical model., {"references":["S.A. Campbell, D.C. Gilmer, X. Wang, M. Hsieh, H-S. Kim, W.L.\nGladfelter and J. Yan , \"MOSFET transistors fabricated with high\npermittivity TiO2 dielectrics\" IEEE Trans. Electron Devices vol. 44,\npp.104-109, (1997).","W. Tsai et a,l \"Performance comparison of sub 1 nm sputtered TiN\nHfO2 nMOS and pMOSFETs\" IEDM Tech., Dig. 311-314, (2003).","H. Kimura, J. Mizuki, S. Kamiyama and H. Suzuki, \"Extended x-ray\nabsorption fine structure analysis of the difference in local structure of\ntantalum oxide capacitor films produced by various annealing methods\"\nAppl. Phys. Lett. Vol. 66, pp.2209-2211, (1995).","J-L Autran, D. Munteanu, M. Houssa, K. C. Coulie and A. Said,\n\"Performance degradation induced by fringing field-induced barrier\nlowering and parasitic charge in double-gate metal-oxide\nsemiconductor field-effect transistors with high-ê dielectrics\" Japan. J.\nAppl. Phys. Vol. 44, 8362-6, (2005).","S.J. Lee, C.H. Choi, A. Kamath, R. Clark and D.L. Kwong, \"\nCharacterization and reliability of dual high-k gate dielectric stack\n(poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for systemon-\nchip applications\" IEEE Electron Device Lett. Vol. 24, 105-107,\n(2003).","T. Kauerauf, B. Govoreanu, R. Degraeve, G. Groeseneken and H. Maes,\n\"Scaling CMOS: finding the gate stack with the lowest leakage current\"\nSolid-State Electron. Vol. 49, 695-701, (2005).","B.Cheng, M. Cao, R. Rao, A. Inani, P.V. Voorde, W.M. Greene, J.M.C.\nStork, Z. Yu, P.M. Zeitoff and J.C.S. Woo , \"The impact of high-k gate\ndielectrics and metal gate electrodes on sub-100 nm MOSFETs\" IEEE\nTrans. Electron. Devices Vol. 46, pp. 1537, (1999).","J. Zhang, J.S. Yuan and Y. Ma \"Modeling short channel effect on highk\nand stacked gate MOSFETs\" Solid-State Electron. Vol.44, pp.\n2089, (2000).","P.Malik, S.P.Kumar, R.Chaujar, M.Gupta, R.S.Gupta, \"GATE\nMATERIAL ENGINEERED-TRAPIZIODAL RECESSED CHANNEL\nMOSFET FOR HIGH-PERFORMANCE ANALOG AND RF\nAPPLICATIONS\", Microwave and optical technology letters, Vol.52,\nmarch 2010.\n[10] P.H. Bricout and E. Dubois \"Short-channel effect immunity and current\ncapability of sub-0.1-micron MOSFETs using a recessed channel\" IEEE\nTrans. Electron. Devices Vol.43, pp.1251 (1996).\n[11] H. Ren and Y. Hao \"The influence of geometric structure on the hotcarrier-\neffect immunity for deep-sub-micron grooved gate PMOSFET\nSolid-State Electron\". Vol.46, pp. 665 (2002).\n[12] ATLAS: 3-D and DEVEDIT: 3D Device Simulator SILVACO\nInternational (2002).\n[13] X.J. Zhang, H.X. Ren, Q. Feng and Y. Hao, Chin. J. Semiconductors,\nVol.25, pp. 441, (2004) (in chinese)\n[14] N.D. Arora, R.Rios, C-L Huang and K. Raol,\"PCIM: A Physically\nShort-Channel IGFET Model for Circuit Simulation\" IEEE Trans.\nElectron Devices, Vol.41, June 1994."]}