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Flash memory is used as a main data storage medium in increasingly large areas of applications, rapidly replacing hard disk drives because of its low power consumption, fast random access, and high shock resistance. Such flash-based storage devices generally incorporate multiple flash memory chips to meet the ever growing capacity demands. Using multiple chips in a single storage device, at the same time, opens an opportunity to boost the performance based on multi-unit parallelism. However, parallel execution of multiple flash operations introduces complications when bad blocks occur, which is unavoidable due to flash memory's physical characteristics. The situation gets even worse when bad block occurrences are accompanied by sudden power failures. We propose a bad block management scheme called P-BMS that can fully utilize flash-level parallelism, while guaranteeing provably correct block replacement. Experiments show that our P-BMS achieves a throughput that is more than 95% of the maximum bandwidth of the flash controller, even with bad block occurrences far heavier than in real flash memory. [ABSTRACT FROM AUTHOR]

In this article, we propose an application-specific demand paging mechanism for low-end embedded systems that have flash memory as secondary storage. These systems are not equipped with virtual memory. A small memory space called an execution buffer is used to page the code of an application. An application-specific page manager manages the buffer. The page manager is automatically generated by a compiler post-pass optimizer and combined with the application image. The post-pass optimizer analyzes the executable image and transforms function call/return instructions into calls to the page manager. As a result, each function in the code can be loaded into the memory on demand at runtime. To minimize the overhead incurred by the demand paging technique, code clustering algorithms are also presented. We evaluate our techniques with ten embedded applications, and our approach can reduce the code memory size by on average 39.5% with less than 10% performance degradation and on average 14% more energy consumption. Our demand paging technique provides embedded system designers with a trade-off control mechanism between the cost, performance, and energy efficiency in designing embedded systems. Embedded system designers can choose the code memory size depending on their cost, energy, and performance requirements. [ABSTRACT FROM AUTHOR]

As the multimedia handheld devices using NAND flash memory as storage media is becoming more popular, the importance of the flash file system is increasing. Although there has been substantial research on file systems dedicated to NAND flash memory, little attention has been paid to legacy file systems running on top of NAND flash memory. In this paper, we propose an anti-fragmentation cluster allocation (AFCA) scheme for the Linux Ext2 file system. For the proposed scheme, we re-define the concept of file system fragmentation that takes into account the characteristics of NAND flash memory. The proposed AFCA scheme tries to minimize the performance degradation resulting from the fragmentation problem by discriminately allocating free clusters to files depending on their size relative to the flash memory block size. Evaluation results show that compared to the original cluster allocation scheme in Ext2, the proposed AFCA scheme significantly reduces the file system fragmentation according to the new definition and improves the file system performance, especially the write performance, by up to 43%. [ABSTRACT FROM AUTHOR]

Real-time embedded systems are typically constrained in terms of three system performance criteria: space, time, and energy. The performance requirements are directly translated into constraints imposed on the system's resources, such as code size, execution time, and energy consumption. These resource constraints often interact or even conflict with each other in a complex manner, making it difficult for a system developer to apply a well-defined design methodology in developing a real-time embedded system. Motivated by this observation, we propose a design framework that can flexibly balance the tradeoff involving the system's code size, execution time, and energy consumption. Given a system specification and an optimization criteria, the proposed technique generates a set of design parameters in such a way that a system cost function is minimized while the given resource constraints are satisfied. Specifically, the technique derives code generation decision for each task so that a specific version of code is selected among a number of different ones that have distinct characteristics in terms of code size and execution time. In addition, the design framework determines the voltage/frequency setting for a variable voltage processor whose supply voltage can be adjusted at runtime in order to minimize the energy consumption while execution performance is degraded accordingly. The proposed technique formulates this design process as a constrained optimization problem. We show that this optimization problem is NP-hard and then provide a heuristic solution to it. We show that these seemingly conflicting design goals can be pursued by using a simple optimization algorithm that works with a single optimization criteria. Moreover, the optimization is driven by an abstract system specification given by the system developer, so that the system development process can be automated. The results from our simulation show that the proposed algorithm finds a solution that is close to the optimal one with the average error smaller than 1.0%. [ABSTRACT FROM AUTHOR]

Flash memory solid state disk (SSD) is gaining popularity and replacing hard disk drive (HDD) in mobile computing systems such as ultra mobile PCs (UMPCs) and notebook PCs because of lower power consumption, faster random access, and higher shock resistance. One of the key challenges in designing a high-performance flash memory SSD is an efficient handling of small random writes to non-volatile data whose performance suffers from the inherent limitation of flash memory that prohibits in-placc update. In this paper, we propose a high performance Flash/FRAM hybrid SSD architecture called Chameleon. In Chameleon, metadata used by the flash translation layer (FTL), a software layer in the flash memory SSD, is maintained in a small FRAM since this metadata is a target of intensive small random writes, whereas the bulk data is kept in the flash memory. Performance evaluation based on an FPGA implementation of the Chameleon architecture shows that the use of FRAM in Chameleon improves the performance by 21.3 %. The results also show that even for bulk data that cannot be maintained in FRAM because of the size limitation, the use of fine-grained write buffering is critically important because of the inability of flash memory to perform in-placc update of data. [ABSTRACT FROM PUBLISHER]

Interoperability is an important requirement for portable storage devices that are increasingly being used to exchange and share data among diverse hosts. However, interoperability cannot be provided if different host systems use different file systems. To address this problem, we propose a storage device that contains a file system within itself, which we refer to as FSOC (File System On Chip). In this paper, we explain the design and implementation of a Flash memory-based FSOC as a proof-of-concept. We also propose a performance model for FSOC, which is derived by analyzing operations of the host and storage device. Using this model, we show that aside from qualitative benefits, there are quantitative benefits in using FSOC instead of a conventional storage device. Results from a series of experiments are given that compare the performance of a conventional storage device and the FSOC using synthetic workloads as well as real applications, which verifies the proposed model. [ABSTRACT FROM AUTHOR]

Presents a study that described a buffer replacement scheme, called Detection-based Adaptive Replacement (DEAR), for effective caching of disk blocks in a computer operating system. Features of the DEAR scheme; Implementation of the DEAR scheme in the FreeBSD operating system; Evaluation of the performance of the DEAR scheme.

Proposes a flash translation layer (FTL) design aimed at mass storage CompactFlash systems. Characteristics of flash memory that make difficult straightforward replacement of magnetic disks; Background flash memory; Description of the log block scheme proposed; Evaluation of the proposed FTL design.

Shows that there exists a spectrum of block replacement policies in computer memory that subsumes the two seemingly unrelated and independent Least Recently Used (LRU) and Least Frequently Used (LFU) policies. Spectrum of implementations of the LRFU that again subsumes the LRU and LFU implementations; Comparison of the LRFU policy with other policies; Combined effects of λ and correlated period on the performance of the LRFU policy.

Proposes a call admission control scheme for low earth orbit satellite networks. Purpose of the scheme; Call traffic recasting; Traffic projections.

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach. [ABSTRACT FROM AUTHOR]

Proposes a framework for solving the link assignment problem associated with the use of intersatellite links in low earth orbit satellite networks. Information on the framework; What is allowed by the finite state automation based framework; Details on what is used by Iridium and Calling low earth orbit satellites.

Proposes a technique used in the analysis of cache-related preemption delays in fixed-priority preemptive scheduling. Steps which the techniques consists of; Information on real-time systems; Schedulability analysis in fixed-priority scheduling; Details on caches in real-time systems.