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The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/ $\mu$m for 1.0 V and 2.52 mA/ \mu$m for 1.8 V gate overdrive with an off-current set at 100 nA/\mu$m. On- to off-current ratios above 10^8C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength. [ABSTRACT FROM PUBLISHER]

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs. [ABSTRACT FROM AUTHOR]

In this paper, we report the first systematic study of quantum transport simulation of the impact of precisely positioned dopants on the performance of ultimately scaled gate-all-around silicon nanowire transistors (NWTs) designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space nonequilibrium Green function formalism is used. The simulations are carried out for an n-channel NWT with \2.2 \times \2.2\ \nm^2 cross section and 6-nm channel length, where the locations of the precisely arranged dopants in the source–drain extensions and in the channel region have been varied. The individual dopants act as localized scatters, and hence, impact of the electron transport is directly correlated to the position of the single dopants. As a result, a large variation in the on-current and a modest variation of the subthreshold slope are observed in the ID–VG characteristics when comparing devices with microscopically different discrete dopant configurations. The variations of the current–voltage characteristics are analyzed with reference to the behavior of the transmission coefficients. [ABSTRACT FROM AUTHOR]