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LED lighting has become the standard solution for illumination purposes thanks to its energy efficiency. Nowadays, there is growing interest in the use of LEDs for data transmission to develop future-generation communication systems. The low cost and widespread deployment of phosphor-based white LEDs make them the best candidate for visible light communications (VLC), although they have a limited modulation bandwidth. This paper presents a simulation model of a VLC link based on phosphor-based white LEDs and a method to characterize the VLC setup used to perform the data transmission experiments. Specifically, the simulation model incorporates the frequency response of the LED, the noise levels coming from the lighting source and the acquisition electronics, and the attenuation due to both the propagation channel and the angular misalignment between the lighting source and the photoreceiver. In order to validate the suitability of the model for VLC, carrierless amplitude phase (CAP) and orthogonal frequency division multiplexing (OFDM) modulation signals were employed for data transmission, and simulations with the proposed model and measurements over the equivalent scenario show high agreement. [ABSTRACT FROM AUTHOR]

The widespread deployment of LEDs for illumination purposes has open the door to the use of these devices for visible light communications (VLC). Most lighting fixtures are mounted with phosphor-based white LEDs, and a driver connected to the LED is also required for VLC. This paper shows that the parasitic effects introduced by this setup change the frequency response of the intrinsic LED. A linear model to characterize the whole setup is proposed, as well as a methodology to extract its parameters. This methodology allows the designer to characterize the frequency response of LEDs without the additional difficulty of knowing the specific parasitic components introduced by the setup. The proposed model offers an accurate estimation of the slope of the LED frequency response in order to broaden the frequency range in which the model is useful to characterize and simulate VLC links. This was corroborated with the characterization of three commercial white LEDs whose measured and modeled frequency responses matched perfectly. [ABSTRACT FROM AUTHOR]

This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students. Index Terms--Arithmetic, coordinate rotation digital computer (CORDIC), decimate filters, digital circuits, digital signal processing (DSP), direct digital synthesis (DDS), fast Fourier transform (FFT), field-programmable gate arrays (FPGA) implementation, logic design, mixer, real-time applications, signal processing, spectrum analyzer, windowing.

This paper presents an efficient implementation of digit-serial/parallel multipliers on 4-input look-up table (LUT)-based field programmable gate arrays (FPGAs). This subset of FPGA devices hide individual gate delays and add important wiring delay. These two facts produce important changes over the theoretical advantages of each topology. Architectural transformations are applied to obtain topologies with minimum logic depth and where the maximum clock speed is limited by the FPGA technology. The main results of applying those transformations to the different multipliers have been quantified for Altera FLEX10K family, and the conclusions have been extrapolated to other FPGA families. Index Terms--Digit-serial arithmetic, field programmable gate arrays (FPGAs), serial/parallel multiplier.

Recently, Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was proposed to achieve high spectral efficiency in intensity-modulator direct-detection optical links. This paper shows that the HC-SCM scheme has a high computational load and proposes the rational Oversampled Subcarrier Modulation (OVS-SCM) as a computational efficient alternative that, furthermore, improves the spectral efficiency. The presented experimental results show that our 256-QAM proposal allows to transmit below the hard-decision forward error correction, with a throughput of 17.8 Gb/s in a 2.5 GHz bandwidth, and a spectral efficiency of 7.2 b/s/Hz, through 20 km of single-mode optical fiber. [ABSTRACT FROM AUTHOR]

This article presents a new entry to the class of published algorithms for the fast computation of the arctangent of a complex number. Our method uses a look-up table (LUT) to reduce computational errors. We also show how to convert a large-sized LUT addressed by two variables to an equivalent-performance smaller-sized LUT addressed by only one variable. In addition, we demonstrate how and why the use of follow-on LUTs applied to other simple arctan algorithms produce unexpected and interesting results. [ABSTRACT FROM PUBLISHER]

The computation of the arctangent of a complex number, i.e., the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In this brief, we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a first stage that performs a coarse approximation of the atan2 function and a second stage that improves the output accuracy by means of a lookup table. We present results for fixed-point implementations in a field-programmable gate array device, all of them guaranteeing last-bit accuracy, which provide an advantage in latency, speed, and use of resources, when compared with well-established fixed-point options. [ABSTRACT FROM PUBLISHER]

Nonbinary LDPC codes outperform their binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node (CN) processor, for high-order Galois fields (GFs) higher than GF(16). To overcome this drawback, we propose an approximation for the trellis min–max algorithm that allows us to reduce the number of exchanged messages between the CN and the variable node compared with previous proposals from the literature. On the other hand, we reduce the complexity in the CN processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90-nm CMOS technology for the (837, 723) NB-LDPC code over GF(32) and the (1536, 1344) over GF(64), achieving an area saving of 16% and 36% for the CN and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 and 1.26 Gb/s, which outperforms the state of the art of high-rate decoders with the high GF order from the literature. [ABSTRACT FROM PUBLISHER]

This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32) and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). In addition, a layered decoder architecture is presented and implemented on a 90-nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF(16), (837, 726) over GF(32), and (1536, 1344) over GF(64). In all cases, the achieved throughput is higher than 1 Gb/s. [ABSTRACT FROM PUBLISHER]

In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged between one check node and the connected variable nodes from dc \times q to $5 \times q$ , and its application has a high impact on the performance of the decoder: the storage and routing areas are reduced and the throughput is increased. Unlike other methods, CNBMP does not introduce any approximation or modification in the information and the processed operations are exactly the same as those of the original decoders; hence, no performance degradation is introduced. To demonstrate its advantages, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were also reduced from dc \times q to $5 \times q$ . This architecture was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an area of 10.67 mm2, which is 3.9 more efficient than the best solution found in the literature. [ABSTRACT FROM PUBLISHER]

In this paper a low-complexity time synchronization algorithm for optical orthogonal frequency division multiplexing (OFDM) is proposed. The algorithm is based on a repetitive preamble that allows the use of a short cross correlator with an exponential average filter for postprocessing before a threshold detection. The signals in the correlation have been quantized with 1 bit, and the correlations have been implemented as a hard-wired tree adder to reduce the hardware cost. This solution has been verified in a passive optical network (PON) system using a directly modulated distributed feedback (DFB) laser achieving excellent performance with low computing processing complexity even in low signal-to-noise ratio scenarios. Finally, a parallel hardware architecture has been proposed for this time synchronization algorithm, and it has been implemented in a field programmable gate array device reaching a sample rate throughput up to 7.4 Gs?s. [ABSTRACT FROM PUBLISHER]

Nonbinary low-density parity-check (NB-LDPC) codes have become an efficient alternative to their binary counterparts in different scenarios, such as moderate codeword lengths, high-order modulations, and burst error correction. Unfortunately, the complexity of NB-LDPC decoders is still too high for practical applications, especially for the check node (CN) processing, which limits the maximum achievable throughput. Although a great effort has been made in the recent literature to overcome this disadvantage, the proposed decoders are still not ready for high-speed implementations for high-order fields. In this paper, a simplified trellis min–max algorithm is proposed, where the CN messages are computed in a parallel way using only the most reliable information. The proposed CN algorithm is implemented using a horizontal layered schedule. The overall decoder architecture has been implemented in a 90-nm CMOS process for a ( $N=837$ and $K=726$ ) NB-LDPC code over GF(32), achieving a throughput of 660 Mb/s at nine iterations based on postlayout results. This decoder increases hardware efficiency compared with the existing recent solutions for the same code. [ABSTRACT FROM AUTHOR]

A multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering the multiplicity of the candidates at the check-node output, to perform a more accurate symbol-flipping decision at the variable node update. The MV-SF algorithm greatly improves the frame error rate performance of GBFDA and approaches the performance of the best state-of-the-art decoders [extended min-sum and min-max (Min–Max)] with lower complexity. For a $(N=837,K=723)$ NB-LDPC code over GF(32), the decoder derived from the proposed algorithm can reach a throughput higher than 500 Mb/s and a coding gain of 0.44 dB compared with the most efficient GBFDA architecture with only twice the silicon area. Our architecture has 27% efficiency gain compared with the best Min–Max architecture found in the literature, with a performance loss of just 0.21 dB at frame error rate 10^{-4} . [ABSTRACT FROM AUTHOR]

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not only to save memory, but also to reduce the number of arithmetic resources needed. In addition, a new initialization of the algorithm avoids using techniques to control data growth without any performance degradation, reduces routing, increasing the maximum frequency achievable, and saves logic. The decoder derived from the simplified algorithm requires almost half the area of previous architectures, with a throughput of 716 Mbps on a 90-nm CMOS process for the (837, 723) nonbinary code over GF(32) at ten iterations. [ABSTRACT FROM AUTHOR]

In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature) with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel. [ABSTRACT FROM AUTHOR]

WLAN standards make use of different transmission modes to cope with different channel conditions, these modes make use of different modulation constellations and code rates. Data encoding is done with a 64-state convolutional code of rate 1/2, some modes employ this basic rate and others puncture the encoded data to obtain a rate of 3/4. At the receiver, the decision depth needed by the Viterbi decoder is higher for decoding punctured modes than for decoding non-punctured modes, this means that punctured modes need a greater area and, then, they cause a higher power consumption. This fact is used in this letter to reduce the power consumption of the Viterbi decoder when dealing with half-rate code modes, an architecture that disables the unnecessary hardware in the non-punctured modes allows a reduction of 20% in the dynamic power consumption with an area increase of only 1%. [ABSTRACT FROM AUTHOR]

CORDIC is a versatile algorithm widely used for VLSI implementation of digital signal processing applications. This article presents a tutorial of how to use CORDIC to implement different communication subsystems that can be found in a software defined radio. Specifically, it shows how to use CORDIC to implement direct digital synthesizers, AM, PM, and FM analog modulators and ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, full mixers for complex signals, and phase detection for synchronizers. The article also shows some tricks to efficiently implement the algorithm. [ABSTRACT FROM AUTHOR]

In this work, we present a new architecture for soft-decision Reed–Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of α that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a η = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true η = 5 and η = 6 LCC decoders, respectively. For example, our η = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder. [ABSTRACT FROM AUTHOR]

A symbol-reliability based decoding algorithm with serial schedule for non-binary low-density parity-check (LDPC) codes is presented. Performance results, together with implementation complexity analysis, are provided for different sample codes. The proposed algorithm achieves a similar gain to the min-max algorithm for codes with column weight dv ≥ 6, with lower complexity than previous symbol-reliability based algorithms. [ABSTRACT FROM PUBLISHER]

This paper presents the hardware architecture of an OFDM receiver suitable for optical communications. The receiver has been implemented in an FPGA device and used to demonstrate experimentally an optical OFDM transmission in a passive optical link with a directly modulated DFB laser and DAC/ADC at 5 GS/s. A bit rate of 20.37 Gb/s is achieved using an OFDM signal with subcarrier modulation format up to 512-QAM, it has been successfully transmitted over 10 km SSMF with a spectral efficiency of 8.38 bit/s/Hz.