40 results on '"Valls, Javier"'
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2. Acoustic detection of the effects of prolonged fasting on newly hatched broiler chickens
3. FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems
4. Reed–Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems
5. Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links.
6. FPGA implementation of an OFDM-based WLAN receiver
7. Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles
8. Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes
9. Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes
10. 50 years of CORDIC: algorithms, architectures, and applications
11. Linear Response Modeling of High Luminous Flux Phosphor-Coated White LEDs for VLC.
12. FFT spectrum analyzer project for teaching digital signal processing with FPGA devices
13. Evaluation of CORDIC Algorithms for FPGA Design
14. Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers
15. A Computational Efficient Nyquist Shaping Approach for Short-Reach Optical Communications.
16. The use of Cordic software defined radios: a tutorial
17. Fast- and Low-Complexity atan2(a,b) Approximation [Tips and Tricks].
18. A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed–Solomon Decoding.
19. A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number.
20. Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm.
21. High-Performance NB-LDPC Decoder With Reduction of Message Exchange.
22. Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages.
23. Low-complexity time synchronization algorithm for optical OFDM PON system using a directly modulated DFB laser.
24. A symbol flipping decoder for NB-LDPC relying on multiple votes.
25. Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes.
26. Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes.
27. Low latency T-EMS decoder for non-binary LDPC codes.
28. High-throughput FPGA-based emulator for structured LDPC codes.
29. Decoder for an enhanced serial generalized bit flipping algorithm.
30. Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard.
31. Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.
32. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain.
33. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes.
34. POWER CONSUMPTION REDUCTION IN A VITERBI DECODER FOR OFDM-WLAN.
35. The Use of CORDIC in Software Defined Radios: A Tutorial.
36. Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor.
37. Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code.
38. Diferentes sistemas sanitarios.
39. Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.
40. Real-time 20.37 Gb/s optical OFDM receiver for PON IM/DD systems.
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