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Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit.sup.1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering.sup.2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces.sup.4 or bulk copper foils.sup.5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films.sup.6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111).sup.5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics. The epitaxial growth of single-crystal hexagonal boron nitride monolayers on a copper (111) thin film across a sapphire wafer suggests a route to the broad adoption of two-dimensional layered semiconductor materials in industry., Author(s): Tse-An Chen [sup.1] , Chih-Piao Chuu [sup.1] , Chien-Chih Tseng [sup.2] , Chao-Kai Wen [sup.2] , H.-S. Philip Wong [sup.1] , Shuangyuan Pan [sup.3] , Rongtan Li [sup.4] [sup.5] [...]

Semiconducting single‐walled carbon nanotube (CNT) is a promising candidate as a channel material for advanced logic transistors, attributed to the ultra‐thin 1‐nm cylindrical geometry, high mobility, and high carrier injection velocity. However, the presence of undesired CNT bundles in the CNT arrays for wafer‐scale device fabrication, even when utilizing the state‐of‐the‐art dimension‐limited self‐alignment (DLSA) method, poses challenges. These CNT bundles degrade the transistor gate's efficiency in controlling the flow of charge carriers in the CNT channel, leading to pronounced device‐to‐device variability. Here, a novel method is introduced to alleviate bundling in CNT arrays assembled via DLSA, by involving small molecule additive to screen the attractive van der Waals force between neighboring CNTs during the DLSA process, resulting in over 50% reduction in CNT bundling. Furthermore, a pioneering methodology for quantifying CNT bundles is presented and employed experimentally to assess bundles in dense CNT arrays assembled by DLSA using transmission electron microscopy. Both experimental data and molecular dynamics simulation reveal that CNT bundling originates from van der Waals attraction between CNTs, and the disturbed liquid‐liquid interface by accumulating excess polar molecules. These findings illuminate new pathways for realizing dense, bundle‐free CNT arrays. [ABSTRACT FROM AUTHOR]

The development of silicon semiconductor technology has produced breakthroughs in electronics--from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones--by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented., Author(s): Deji Akinwande [sup.1] , Cedric Huyghebaert [sup.2] , Ching-Hua Wang [sup.3] , Martha I. Serna [sup.1] , Stijn Goossens [sup.4] , Lain-Jong Li [sup.5] , H.-S. Philip Wong [sup.3] [...]

Author(s): Max M. Shulaker (corresponding author) [1, 2]; Gage Hills [1]; Rebecca S. Park [1]; Roger T. Howe [1]; Krishna Saraswat [1]; H.-S. Philip Wong [1]; Subhasish Mitra [1, 3] [...]

Carbon nanotubes (CNTs) have great potential for future high-performance and energy-efficient transistor technology. To realize this potential, methods to dope the CNTs need to be developed to achieve low parasitic resistance of the transistor. Two key issues present themselves: (a) understanding the doping mechanism of the various methods and (b) stability of the doping method. For instance, although studies on molybdenum oxide (MoOx) demonstrate its ability to heavily dope nanomaterials, the interaction between MoOx and the CNT is unclear. Here, we observe an unstable effect of MoOx on the CNT and demonstrate dielectric passivation as a means to preserve the doping strength. The semiconducting CNTs exhibit greater than 103× reduction in resistance after stably doped with MoOx. By exploiting the instability of MoOx, we delve deeper into clarifying the doping mechanism. The relationship between the time-dependent material property of MoOx and the change in the electrical measurements of CNT devices is investigated to study the role of work function in doping the CNTs. We conclude that the doping mechanism of MoOx on the CNT is due to bandgap modulation by charge transfer, which occurs due to the difference in work function between MoOx and the CNT. [ABSTRACT FROM AUTHOR]

Phase Change Memory (PCM) is a leading candidate for next generation data storage, but it typically suffers from high switching (RESET) current density (20–30 MA/cm2). Interfacial Phase Change Memory (IPCM) is a type of PCM using multilayers of Sb2Te3/GeTe, with up to 100× lower reported RESET current compared to the standard Ge2Sb2Te5-based PCM. Several hypotheses involving fundamentally new switching mechanisms have been proposed to explain the low switching current densities, but consensus is lacking. Here, we investigate IPCM switching by analyzing its thermal, electrical, and fabrication dependencies. First, we measure the effective thermal conductivity (∼0.4 W m−1 K−1) and thermal boundary resistance (∼3.4 m2 K GW−1) of Sb2Te3/GeTe multilayers. Simulations show that IPCM thermal properties account only for an ∼13% reduction of current vs standard PCM and cannot explain previously reported results. Interestingly, electrical measurements reveal that our IPCM RESET indeed occurs by a melt-quench process, similar to PCM. Finally, we find that high deposition temperature causes defects including surface roughness and voids within the multilayer films. Thus, the substantial RESET current reduction of IPCM appears to be caused by voids within the multilayers, which migrate to the bottom electrode interface by thermophoresis, reducing the effective contact area. These results shed light on the IPCM switching mechanism, suggesting that an improved control of layer deposition is necessary to obtain reliable switching. [ABSTRACT FROM AUTHOR]

Resistance drift in phase change memory (PCM) reduces the accuracy of analog computing applications such as neural network inference. Recently, PCMs based on superlattice (SL) phase change layers have shown low resistance drift, however the origin of this low drift remains unexplored. Here, we uncover that resistance drift in SL-PCM based on alternating layers of Sb2Te3 and Ge2Sb2Te5 (GST) is controlled by the number of SL interfaces as well as the degree of SL intermixing. Temperature-dependent measurements reveal smaller and more stable activation energy upon annealing (thus suppressed structural relaxation) in our SL-PCM vs. control GST devices, accounting for the low resistance drift. By controlling SL interfaces, we achieve low resistance drift coefficient ${v} < 0.01$ in these SL-PCMs, maintained after extensive cycling and at various read voltages and intervals - showing robustness required for analog computing with PCM. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects ION-IOFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between ION and IOFF for digital logic in advanced technology nodes. [ABSTRACT FROM AUTHOR]

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energydelay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies (1,2). Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems (3,4)., CNTs are hollow, cylindrical nanostructures composed of a single sheet of carbon atoms, and have exceptional electrical, physical and thermal properties (5-7). They can be used to fabricate CNT field-effect [...]

Several device simulation and circuit analysis approaches are employed to explain the impact of parasitic resistance and capacitance on the performance of the InGaAs high-electron mobility transistor (HEMT) digital logic circuits. The scaled HEMTs are shown to exhibit better performance, as compared to the other experimental devices.

The performance analysis of a prototype 0.25 [mu]m CMOS digital integrated circuit with select horizontal multiwall carbon nanotube (MWCNT) interconnects is presented. The developed framework is found to be powerful nanoelectronic tool that could evaluate various CNT- or nanowire-based interconnects in a realistic integrated-circuit environment.

Ferroelectric switching is demonstrated in CeO2‐doped Hf0.5Zr0.5O2 (HZCO) thin films with application in back‐end‐of‐line compatible embedded memories. At low cerium oxide doping concentrations (2.0–5.6 mol%), the ferroelectric orthorhombic phase is stabilized after annealing at temperatures below 400 °C. HZCO ferroelectrics show reliable switching characteristics beyond 1011 cycles in TiN/HZCO/TiN capacitors, several orders of magnitude greater than identically processed Hf0.5Zr0.5O2 (HZO) capacitors, without sacrificing polarization and retention. Internal photoemission and photoconductivity experiments show that CeO2‐doping introduces in‐gap states in HZCO that are nearly aligned with TiN Fermi level, facilitating electron injection through these states. The enhanced average bulk conduction, which may lead to more uniform thermal dissipation in the HZCO films, delays irreversible degradation via breakdown that leads to device failure after repeated programming cycles. [ABSTRACT FROM AUTHOR]