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A 320 $\times $ 240 indirect time-of-flight (i-ToF) image sensor with a 5.6- $\mu \text{m}$ two-tap 1.5-V pump gate modulation pixel has been designed. Novel characteristics, such as the optimized pinned layer doping and potential buffer region (PBR) structure with pump gate modulator (PGM), are proposed to achieve a maximum lateral modulation electric field of 1500 V/cm under the front-side illumination (FSI) process. As a result, the proposed time-of-flight (ToF) sensor shows 200-mW power consumption and 54% demodulation contrast (DC) at 50-MHz modulation frequency, depth noise less than 1% with 940-nm illuminator from 0.3 to 3 m. [ABSTRACT FROM AUTHOR]

Low-frequency electronic noise is an important parameter used for the electronic and sensing applications of transistors. Here, we performed a systematic study on the low-frequency noise mechanism for both p-channel and n-channel MoTe2 field-effect transistors (FET) at different temperatures, finding that low-frequency noise for both p-type and n-type conduction in MoTe2 devices come from the variable range hopping (VRH) transport process where carrier number fluctuations (CNF) occur. This process results in the broad distribution of the waiting time of the carriers between successive hops, causing the noise to increase as the temperature decreases. Moreover, we found the noise magnitude for p-type MoTe2 FET hardly changed after exposure to the ambient conditions, whereas for n-FET, the magnitude increased by nearly one order. These noise characteristics may provide useful guidelines for developing high-performance electronics based on the emerging transition metal dichalcogenides. [ABSTRACT FROM AUTHOR]

Multivoltage domains are urgently needed in modern system on chips (SoCs), while existing solutions such as switched dc−dc converter, switched capacitor converter, and low-dropout regulator (LDO) do not generate multivoltage domains conveniently and inexpensively. This article presents a highly efficient fully integrated power management strategy to provide the multiple voltage domains. The proposed architecture stacks a main LDO and several auxiliary push−pull regulators (APPRs) to generate multiple voltages for various loads in one SoC chip. The APPR regulates the load current by either absorbing or providing the additional current, which stabilizes the output voltages, increases the power supply rejection (PSR) and decreases the cross-regulation. A prototype with two output terminals is implemented with a standard 0.18-μm CMOS technology. The whole system achieves high power efficiency of 96.5% and high PSR of −62 and −142 dB for upper and lower outputs, respectively. The chip area is 980 μm × 500 μm and the total quiescent current is 239 μA. In addition, all off-chip components are eliminated, which is favorable for monolithic realization. The reduced system cost and the reduced electromagnetic interference also simplify the power management significantly, which helps to enable low-power and compact SoCs. [ABSTRACT FROM AUTHOR]

Multiple loops have been used extensively to enhance the system performance in various applications. However, the increasing complexity of multi-loop systems also makes them much more difficult to analyze and implement. In this paper, a new methodology to analyze multi-loop system is proposed. In the proposed framework, multi-loop systems are regarded to be built upon of sub-modules of cascade, parallel adding, and feedback units, and then, they are simplified following a certain procedure based on the correlation of the Bode characteristics of the segmented sub-modules. Applying this methodology, the Bode plot and the transfer function of the system can be easily obtained with the system properties of gains, zeros, and poles. Two examples are provided as demonstrators, including a multi-loop low-dropout regulator (LDO) from literature, and a newly designed multi-loop LDO aiming at enhancing the stability over a wide load range, which show that the Bode plot and the transfer function can be obtained more intuitively and rapidly. Excellent agreements among theory, simulations, and measurements are confirmed, which verify the proposed method. It can help designers to gain more intuitions and insights on multi-loop systems from both circuit and device perspectives, which is also an effective tool for both stability analysis and circuit design. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive delay time control (ADTC)-based CMOS active rectifier is proposed. Compared with previous active rectifiers, power-hungry comparators are eliminated in this structure. Instead, optimal on/off time of the power switches is generated by two current controlled delay lines (CCDLs), which enables drastic power reduction of the active rectifier. In addition, the multiple-pulsing problem is eliminated due to the introduced control mechanism. The high-precision on/off control at picosecond-level precision removes the reverse current of the rectifier and guarantees high voltage conversion rate (VCR) and power conversion efficiency (PCE). The active rectifier is fabricated with a standard 0.18- $\mu \text{m}$ CMOS process. The experimental results show that the quiescent power consumption of the rectifier is less than 230 $\mu \text{W}$. The current conduction angle reaches the optimal state under different input and load conditions because of the adaptive adjustment. The peak PCE is 94.1% at the output power of 10.63 mW. The PCE is enhanced by 6.7% compared with the previous design. The maximum output power of 34.1 mW is achieved with input ac amplitude of 2.5 V. The proposed low-power high-efficiency active rectifier gives a favorable solution for the wireless power transmission systems. [ABSTRACT FROM AUTHOR]

Soft-start strategy is very important for boost converters to guarantee the stability of the output voltage. However, previous methods may cause large initial inrush current and long output voltage settling time. In this paper, a variable ramp-slope with predefined voltage (VRSPV) soft-start strategy is proposed. As a result, one branch of the initial inrush current is successfully eliminated and the output settling time of the boost converter is shortened by using the variable slope soft-start voltage. Also, an adaptive inrush current suppressing (AICS) technique is designed. The series resistance of the output capacitor is adaptively regulated by AICS technique to further suppress the initial inrush current. Finally, the VRSPV strategy and AICS technique are combined and implemented in a voltage-mode boost converter. The measurement results show that the peak initial inrush current and settling time are decreased by 60% and 40%, respectively. The output voltage of the boost converter increases smoothly during the soft-start period and finally achieves stability. The proposed method of combining VRSPV strategy and AICS technique is very suitable to be integrated on a chip to save the printed circuit board area and cost. [ABSTRACT FROM AUTHOR]