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In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

Abstract: Memristive devices acting as high‐performance in‐memory computing fabrics have attracted much attention for nonvolatile parallel architectures to break the von Neumann bottleneck. Here, for the first time, a nonvolatile digital logic system with three‐terminal Pt/SiO2/Pt/Ag/GeTe/Ta one‐memristor‐one‐resistor (1M1R) structure is presented. Programmable nonvolatile Boolean logic gates and clocked sequential logic blocks including D latch and D flip‐flop are experimentally implemented, based on which a 4‐bit linear‐feedback shift register with timing design is functionally verified in simulation. With information generation, processing, transmission, and storage performing within the same 1M1R‐based logic blocks, these results consolidate the feasibility of building memristive digital computing system for future non‐von Neumann computing. [ABSTRACT FROM AUTHOR]

Abstract: The synaptic weight modification depends not only on interval of the pre‐/postspike pairs according to spike‐timing dependent plasticity (classical pair‐STDP), but also on the timing of the preceding spike (triplet‐STDP). Triplet‐STDP reflects the unavoidable interaction of spike pairs in natural spike trains through the short‐term suppression effect of preceding spikes. Second‐order memristors with one state variable possessing short‐term dynamics work in a way similar to the biological system. In this work, the suppression triplet‐STDP learning rule is faithfully demonstrated by experiments and simulations using second‐order memristors. Furthermore, a leaky‐integrate‐and‐fire (LIF) neuron is simulated using a circuit constructed with second‐order memristors. Taking the advantage of the LIF neuron, various neuromimetic dynamic processes, including local graded potential leaking out, postsynaptic impulse generation and backpropagation, and synaptic weight modification according to the suppression triplet‐STDP rule, are realized. The realized weight‐dependent pair‐ and triplet‐STDP rules are clearly in line with findings in biology. The physically realized triplet‐STDP rule is powerful in developing direction and speed selectivity for complex pattern recognition and tracking tasks. These scalable artificial synapses and neurons realized in second‐order memristors can intrinsically capture the neuromimetic dynamic processes; they are the promising building blocks for constructing brain‐inspired computation systems. [ABSTRACT FROM AUTHOR]

Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic. [ABSTRACT FROM PUBLISHER]

Summary The development of effective Mycobacterial antigen diagnostic reagents remains a high priority. The 6-kDa early secreted antigenic target (ESAT6) and 10-kDa culture filtrate protein (CFP10) are secreted early by virulent Mycobacterium tuberculosis ( M. tb ) and are not present in the non-virulent Bacillus Calmette–Guerin (BCG). In this study, we used a Systematic Evolution of Ligands by Exponential Enrichment (SELEX) technique to screen for a functional ssDNA aptamer “antibody” that specifically bound to ESAT6-CFP10 (CE) protein. The selected single ssDNA aptamers (CE24 and CE15) demonstrated the highest specificity and binding affinity to CFP10 (CE24: K d = 3.75 × 10 −7 M) and ESAT6 (CE15: K d = 1.6 × 10 −7 M). We further detected CFP10 and ESAT6 proteins in serum samples from active pulmonary tuberculosis (TB) patients, extrapulmonary TB patients and healthy donors by using an enzyme-linked oligonucleotide assay (ELONA). The results showed that the sensitivity and specificity were 100% and 94.1% (using CE24 aptamer-based ELONA) and 89.6% and 94.1% (using CE15 aptamer-based ELONA), respectively. A good correlation was observed between aptamer-based ELONA and T-SPOT TB assay. Thus, our study suggests that CE24 and CE15 have potentially broad applications as early antigen diagnostic agents not only for active pulmonary TB, extrapulmonary TB, but also possibly for latent TB infection and TB with immune-deficiency. [ABSTRACT FROM AUTHOR]

Memristors have emerged as promising candidates for artificial synaptic devices, serving as the building block of brain-inspired neuromorphic computing. In this letter, we developed a Pt/HfOx/Ti memristor with nonvolatile multilevel resistive switching behaviors due to the evolution of the conductive filaments and the variation in the Schottky barrier. Diverse state-dependent spike-timing-dependent-plasticity (STDP) functions were implemented with different initial resistance states. The measured STDP forms were adopted as the learning rule for a three-layer spiking neural network which achieves a 75.74% recognition accuracy for MNIST handwritten digit dataset. This work has shown the capability of memristive synapse in spiking neural networks for pattern recognition application. [ABSTRACT FROM AUTHOR]

Owing to the capability of integrating the information storage and computing in the same physical location, in-memory computing with memristors has become a research hotspot as a promising route for non von Neumann architecture. However, it is still a challenge to develop high performance devices as well as optimized logic methodologies to realize energy-efficient computing. Herein, filamentary Cu/GeTe/TiN memristor is reported to show satisfactory properties with nanosecond switching speed (<60 ns), low voltage operation (<2 V), high endurance (>10 4 cycles) and good retention (>10 4 s @85 °C). It is revealed that the charge carrier conduction mechanisms in high resistance and low resistance states are Schottky emission and hopping transport between the adjacent Cu clusters, respectively, based on the analysis of current-voltage behaviors and resistance-temperature characteristics. An intuitive picture is given to describe the dynamic processes of resistive switching. Moreover, based on the basic material implication (IMP) logic circuit, we proposed a reconfigurable logic method and experimentally implemented IMP, NOT, OR, and COPY logic functions. Design of a one-bit full adder with reduction in computational sequences and its validation in simulation further demonstrate the potential practical application. The results provide important progress towards understanding of resistive switching mechanism and realization of energy-efficient in-memory computing architecture.

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Nonvolatile stateful logic computing in memristors is a promising paradigm with which to realize the unity of information storage and processing in the same physical location that has shown great feasibility for breaking the von Neumann bottleneck in traditional computing architecture. How to reduce the computational complexity of memristor-based logic functions is a matter of concern. Here, based on a general logic expression, we proposed a method to implement the arbitrary logic of complete 16 Boolean logic in two steps with one memristor in the crossbar architecture. A representative functional complete NAND logic is successfully experimentally demonstrated in the filamentary Ag-AgGeTe-Ta memristors to prove the validity of our method. We believe our work may promote the development of the revolutionary logic in memory architectures.