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To minimize dynamic losses in static CMOS circuits, Clock-Gating ist used to disconnect inactive parts of a system from the clock signal. Leakage losses become more dominant in new technologies, which are reduced by Power-Gating. Adiabatic Logic uses a clocked power supply, thus Power- and Clock-Gating can be achived using only one switch. As the switch raises the dissipated energy in on-state, a major concern is the choice and design of the switch topology. In this paper the basics of Power-Clock-Gating (PCG) in adiabatic logic are described, considerations about the choice of a switch topology are made and design rules for the switch are presented. Further, the influences of PCG on the oscillator are shown. [ABSTRACT FROM AUTHOR]

In this paper we discuss the expected impact of quantum effects in nanostructured CMOS circuits. In order to describe transport in mesoscopic electronic systems our group develops a 1-d numerical simulation packet based on the "non equilibrium Green's functions" (NEGF) formalism. By means of the obtained simulation results we develop extended SPICE circuit models. With these SPICE models the influence of quantum effects to the functionality of classical circuit concepts can be studied. Using these results it is our intention to develop circuits with a higher robustness against these quantum effects. For the illustration of our simulation concept we discuss some results of some circuit examples. [ABSTRACT FROM AUTHOR]