FIELD programmable gate arrays, ALGORITHMS, WORD recognition, SIGNAL processing, PARALLEL processing
Abstract
Copyright of Science: Future of Lithuania / Mokslas: Lietuvos Ateitis is the property of Vilnius Gediminas Technical University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
FIELD programmable gate arrays, DETECTORS, SIGNAL-to-noise ratio, ESTIMATION theory, INFORMATION measurement
Abstract
Copyright of Science: Future of Lithuania / Mokslas: Lietuvos Ateitis is the property of Vilnius Gediminas Technical University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
*FIELD programmable gate arrays, *ALGORITHMS, *COMPUTER algorithms, *VHDL (Computer hardware description language), *STREAMING video & television
Abstract
The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF) algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84x84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640x480 pixel camera. [ABSTRACT FROM AUTHOR]