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In state-of-art digital systems the control device, which usually has a sequential structure, is one of the most important units. Moore finite state machine (FSM) is often used to implement such schemes. While implementing a digital system based on FPGA chips at the design stage of the FSM circuit there is a problem of optimizing the characteristics of its circuit. These characteristics include hardware costs (semiconductor element area occupied by the FSM circuit), speed, and power consumption. Methods of solving this problem depend on the features of the FSM and the circuitry. The features of the Moore FSM are 1) the presence of classes of pseudo-equivalent states and 2) the absence of direct dependence of outputs on inputs. Features of FPGA are: 1) the presence of embedded memory blocks EMB, that can be configured, and 2) a very limited number of inputs of the table type LUT (look-up table). This work aims to develop a method for reducing the number of tabular elements in the circuit of Moore FSM, taking into account both the features of the Moore FSM and the circuitry on which the implementation of the digital system control device is realized. A method for optimizing the cost of equipment in the circuit of the Moore FSM, which is implemented on a mixed basis of LUT and EMB elements, is proposed. The method is based on the use of classes of pseudo-equivalent states of the Moore FSM and it is advisable to use it if the developer of the circuit of the control device can use only a limited number of EMB blocks. It is proposed to present the state code in the form of a concatenation of state class codes and element codes of these classes. Such an approach reduces requirements for the number of EMB inputs. The conditions of application of the proposed method are shown. An example of the synthesis of the circuit of the FSM using the proposed method is given. [ABSTRACT FROM AUTHOR]

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