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Clock skew minimization in high speed VLSI synchronous systems is extremely important, and significant research interest in clock distribution networks exists "within both the industrial and academic communities. The large die size, deterioration in interconnect performance in sub_micron process and high frequency makes the clock design and implementation a major challenge. In this paper, we describe an implementation of a multi-level balanced clock-free distribution scheme that improves the performance considerably. The focus of this clock-tree distribution scheme is to.balance the loading and allocate interconnect delay optimally to take advantage of "self_adjusf" aspect of clock tree into account. Optimal delay allocation among the clock nets do not need to balance all the nets, which use more wires and may cause problem in dense chip.