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In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

The fully recessed gate GaN-on-Si MOS-channel HEMTs (MOSc-HEMT) with Back-Barrier (BB) structure gives rise to unexpected threshold voltage (V TH ) behaviors such as V TH increase with decreasing gate length (L G ) (V TH roll-up) and discrepancies between V TH values extracted from I D (V G ) (V TH_IV ) and from C GC (V G ) (V TH_CV ) characteristics. Using TCAD simulations and experimental measurements, we demonstrate that conduction band confinement, especially at gate corners, is responsible for these peculiar V TH behaviors. This band confinement is strengthened by the fully recessed gate configuration coupled with the proximity of a back-barrier.

In this paper, threshold voltage V TH instabilities under positive gate voltage stress (V GStress ) are thoroughly investigated on GaN-on-Si Enhancement-mode MOS-channel HEMTs. An analysis of pBTI transients performed at several V GStress and temperatures (T) reveals two trap populations close to the Al 2 O 3 /GaN interface namely (1) C N acceptors in the GaN substrate, and (2) defects in the Al 2 O 3 gate oxide. Both trap populations lead to V TH instabilities via different underlying mechanisms as evidenced by TCAD simulations. At V GStress TH drifts are ascribed to C N traps ionization localized at 0.8-0.9eV above the valence band (E v ). At higher VGstress, electron trapping also occurs in Al 2 O 3 defects leading to stronger V TH degradation. DC & AC pBTI transients have been modeled using Capture Emission Time (CET) map approach, which allowed the identification of both trap populations. Temperature-dependent CET maps extraction reveals a strong activation of C N traps with temperature, and confirms Arrhenius analysis consistency. This study provides a deep understanding of BTI reliability in GaN-HEMT technologies.

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al 2 O 3 /UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.