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At present, the general fan-out package generally uses the molding process and uses epoxy molding compound (EMC) material to complete the reconstruction of wafer, but it is not friendly to small-size chips and high fan-out ratio packaging types. In order to solve the problem of small size and high fan-out ratio and other fan-out packaging, JCET ADVANCED PACKAGING CO., LTD. introduced a new kind of encapsulation material, and the wafer reconstruction process in the fan out package is accomplished through three basic processes, such as the lamination process, the leveling process and the silicon support process. However, it also faces warpage problems after curing. Excessive warpage poses a significant challenge to subsequent RDL fabrication, mid-testing and process automation. In this paper, the actual process is reasonably assumed and finite element methods are used to study the effects of chip thickness, fan-out area, the encapsulation material properties and support silicon wafer on the warpage after curing. The lamination process is that an airbag slowly squeezes the encapsulation material into the fan-out area, and the pressure of the airbag can be adjusted by the gas in and out. The wafer surface is uneven after the lamination process, so it needs to be leveled by the leveling process. Leveling process is to make the uneven surface smooth by a heavy and proper amount of steel plate. The encapsulation material is soft, so it is necessary to support the silicon wafer in order to enhance the strength of the structure. In this paper, the curing process is divided into two processes: pre curing process and post curing process. The main function of pre curing is to shape the encapsulation material, and then post curing can make the encapsulation material, chip and supporting silicon have a better combination. The lamination, leveling, and silicon support processes do not involve higher temperatures, so it can be assumed that the reconstructed wafer has no residual stress and warpage. In order to save computer resources and shorten the verification period, the geometric model of simulation is simplified under the condition of ensuring accuracy. Through the finite element method to explore the influence of structural characteristics and material characteristics on the wafer warpage, the selection of parameters is determined according to the actual situation, so as to meet the manufacturability of the structure. The results indicate that with the increase of the thickness of the encapsulated material the encapsulation, wafer warpage is gradually increasing, while the encapsulation material with low modulus and small CTE can improve warpage performance. High modulus, thicker support silicon has a significant effect on reducing warpage, and larger CTE support silicon can also effectively reduce wafer warpage because the larger CTE support silicon reduces the degree of mismatch with the encapsulation CTE. Thinner chips and high fan-out areas tend to increase the warpage of the reconstituted wafer. The study of warpage of package structure and material properties can provide theoretical basis for predicting and improving warpage during the design and evaluation phase of the product.

Flip-chip LEDs have attracted more and more attentions for its benefits such as wire-bonding free, can be driven at higher current, and better thermal dispersion capability over horizontal or vertical ones. At the mean while, wafer-level packaging has been recognized as a kind of high productive and low cost packaging methodology for LEDs, and a lot of effort had been devoted for it in LED industry for recent years. As a combination of advanced chip and packaging technology, a kind of silicon based wafer-level packaging technology which integrated with advanced process such as through silicon via (TSV), chip to wafer (C2W), and conformal phosphor for flip-chip LEDs was introduced. The electrical, optical, chromatic and thermal performance of the packaged LEDs which processed based on the 8 inch silicon wafers had been characterized, as well as the reliability had been tested.

WLCSP (wafer level chip scale package) has been well accepted within modern industry which brings not only the reduction of package size, but also good thermal performance vs. more traditional peripherally leaded packages. At the mean time, WLCSP feathers can significantly lower manufacturing costs. One of the barriers for WLCSP package to be accepted in the industry is the lack of existing and mature SMT and PCB technology with more and more tightened pitches of solder balls. Therefore, demands for cost-efficient packages come out when ball pitch is tightened less than 0.4mm. A new package way named Si-BGA is introduced in this paper. This package related process such as RDL and bumping, chip to wafer, flip-chip bonding, and capillary underfill is introduced. The structure of the prototype is characterized and the die level reliability is tested. The Si-BGA package demonstrated good reliability and can be used in low-k products.