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Power integrity analysis is an essential step in power distribution network (PDN) sign-off to ensure the performance and reliability of chips. However, with the growing PDN size and increasing scenarios to be validated, it becomes very time- and resource-consuming to conduct full-stack PDN simulation to check the power integrity for different test vectors. Recently, various works have proposed machine learning–based methods for PDN power integrity prediction, many of which still suffer from large training overhead, inefficiency, or non-scalability. Thus, this article proposed an efficient and scalable framework for the worst-case power integrity prediction, which can handle general tasks including dynamic noise prediction and bump current prediction. The framework first reduces the spatial and temporal redundancy in the PDN and input current vector and then employs efficient feature extraction as well as a novel convolutional neural network architecture to predict the worst-case power integrity. Experimental results show that the proposed framework consistently outperforms the commercial tool and the state-of-the-art machine learning method with only 0.63–1.02% mean relative error and 25–69× speedup for noise prediction and 0.22–1.06% mean relative error and 24–64× speedup for bump current prediction.

Battery-powered mobile devices are typically featured with fast varying workloads and constrained power supply, demanding more efficient run-time power management. In this paper, we propose a DVFS design and simulation framework to explore the design space for DVFS. The framework leverages the existing tool chains and uses several machine learning models to support the architectural simulation and run-time profiling. When using the proposed framework to evaluate different management methods, the proposed deep-reinforcement-learning approach can achieve 5.8-7.3% performance improvement compared with the other alternatives.

A new donor–acceptor type circularly polarized luminescence material has been developed, and a dihedral angle engineering strategy has been demonstrated for the first time to significantly amplify the luminescence dissymmetry factors.

Multi-resonance thermally activated delayed fluorescence (MR-TADF) emitters based on a novel indole-fused BN-heteroarene (InBN) are developed via a π-truncation strategy. Narrowband blue-emitting OLEDs are demonstrated with high EQEs of up to 16.8%.

Electronic Design Automation (EDA) comprises a series of computationally difficult optimization problems that require substantial specialized knowledge as well as a considerable amount of trial-and-error efforts. However, open challenges including long simulation runtime and lack of generalization continue to restrict the applications of existing EDA tools. Recently, learning-based algorithms especially reinforcement learning (RL) have been successfully applied to handle various combinatorial optimization problems by automatically acquiring knowledge from the past experience. In this paper, we formulate the floorplanning problem, the first stage of the physical design flow, as a Markov Decision Process (MDP). An end-toend learning-based floorplanning framework GoodFloorplan is proposed to explore the design space, which combines graph convolutional network (GCN) and RL. Experimental results demonstrate that, compared with state-of-the-art heuristic-based floorplanners, the proposed GoodFloorplan can provide better area and wirelength.

Approximate computing is a promising alternative to improve energy efficiency for IoT devices on the edge. This work proposes a piecewise-linearly-approximated and unbiased floating-point approximate multiplier with run-time configurability. We provide a theoretically sound formulation that turns multiplication approximation to an optimization problem. With the formulation and findings, a multi-level architecture is proposed to easily incorporate run-time configurability and module execution parallelism. Finally, the proposed multiplier is further optimized to reduce the circuit implementation complexity, making the multiplier linearly dependent on the precision requirement, instead of quadratically or exponentially as in prior work. When compared to the prior state-of-the-art approximate floating-point multiplier, ApproxLP [1], the proposed multiplier outperforms in all the aspects including accuracy, area, and delay. By replacing a full-precision floating-point multiplier in GPU, the proposed design can improve the energy efficiency for various edge computing tasks. Even with Level 1 approximation, the proposed multiplier improves energy efficiency up to 20x for machine learning on CIFAR-10, with almost negligible accuracy loss.

Head and neck squamous cell carcinoma (HNSCC) is a common tumour type in otorhinolaryngology, and its occurrence is related to long-term exposure to tobacco and alcohol. Recently, HPV infection has become an increasingly important contributor to HNSCC, and HPV-associated HNSCC has a different clinical course and better prognosis than non-HPV-associated HNSCC. However, the exact molecular mechanism of HNSCC is unclear. Here, we obtained data from The Cancer Genome Atlas (TCGA) and gene expression omnibus (GEO) to analyse the mitophagy process and related influencing factors of HPV-associated HNSCC via the integration of bioinformatics analysis and experimental validation. We found that in HPV-associated HNSCC, process of mitophagy affects tumour development, immune cell infiltration and prognosis. In the mitophagy process of HPV-related HNSCC: NOS2, IL17REL, TMSB15A, TUBB4A and other hub genes showed significantly higher expression levels than in non-HPV-related HNSCC. Furthermore, this was also confirmed by quantitative real-time PCR (qRT‒PCR), which was used to detect the expression of differentially expressed genes in HNSCC tissues. Furthermore, we found that the unique immunological characteristics by expressing CD8+ T cell in a high level in HPV-related HNSCC, and the scores obtained from the score model affected the prognosis of patients. In conclusion, our study revealed the unique biomolecular signature of mitophagy in HPV-associated HNSCC, which may contribute to the development of precise treatment regimens for HPV-associated HNSCC patients.

The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many on-chip applications. Recently through-silicon-via– (TSV) based inductor (also known as a TSV-inductor) with a magnetic core has been proved to be a viable option for the on-chip DC-DC converter. The operating conditions of these inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, there is a critical need to study the design and optimization details of magnetic core TSV-inductors with the unique three-dimensional structure embedding magnetic core. This article aims to provide a clear understanding of the modeling details of a magnetic core TSV-inductor and a design and optimization methodology to assist efficient inductor design. Moreover, a machine learning–assisted model combining physical details and artificial neural network is also proposed to extract the equivalent circuit to further facilitate DC-DC converter design. Experimental results show that the optimized TSV-inductor with the magnetic core and air-gap can achieve inductance density improvement of up to 7.7 \( \times \) and quality factor improvements of up to 1.6 \( \times \) for the same footprint compared with the TSV-inductor without a magnetic core. For on-chip DC-DC converter applications, the converter efficiency can be improved by up to 15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.

As a promising solution to address memory wall, computing in memory (CiM) designs using CMOS or emerging non-volatile memories (NVMs) are proposed to support bit-wise Boolean logic and arithmetic operations. Unlike the conventional executions that read data out of memory, process sequentially and send the outputs back, CiM implementations fully utilize its parallel in-memory bit-wise computation nature and hence reduce the unnecessary data transfer, thereby saving both area and power consumption. This paper proposes CiM designs based on Ferroelectric FETs (FeFETs) for bit-wise Boolean logic and multi-input MAJ operations. By exploiting the merged memory and switch property of FeFETs, our design realizes both high storage density and energy efficiency in computation. Evaluation results demonstrate that our proposed CiM designs can achieve significant energy saving and performance improvement, up to ~31% for Boolean logic and ~11× for majority vote, when compared to other NVM counterparts.

Always-on intelligent visual perception applications are widely deployed in edges in the AIoT era. In order to eliminate power costs of data conversion and transmission, this paper proposes Senputing, an ultra-low-power processing-in-sensor chip that completely fuses sensing and computing together for a BNN-based hierarchical processing system. This chip could operate in two modes. In computation mode, photocurrents are directly utilized for computing without being converted into voltages, and the computation results of 1-st BNN layer are directly sent out to subsequent BNN processors for an always-on coarse classification, eliminating conversion power and storage cost of raw images. Once an interested objected is detected, this chip switches to sensor mode and sends raw images to potential full-precision processors or cloud servers for fine-grained recognition or segmentation. A 32x 32 prototype is fabricated with 180nm CMOS process. It accomplishes MNIST dataset classification task with the accuracy of 93.76% and the power consumption of 147nW at 156fps, achieving 13.1x energy efficiency compared with state-of-the-art work.

Pathology image segmentation is an essential step in early detection and diagnosis for various diseases. Due to its complex nature, precise segmentation is not a trivial task. Recently, deep learning has been proved as an effective option for pathology image processing. However, its efficiency is highly restricted by inconsistent annotation quality. In this article, we propose an accurate and noise-tolerant segmentation approach to overcome the aforementioned issues. This approach consists of two main parts: a preprocessing module for data augmentation and a new neural network architecture, ANT-UNet. Experimental results demonstrate that, even on a noisy dataset, the proposed approach can achieve more accurate segmentation with 6% to 35% accuracy improvement versus other commonly used segmentation methods. In addition, the proposed architecture is hardware friendly, which can reduce the amount of parameters to one-tenth of the original and achieve 1.7× speed-up.

Purpose This study aimed to develop a novel analytic approach based on 2-deoxy-2-[18F]fluoro-D-glucose positron emission tomography/computed tomography ([18F]FDG PET/CT) radiomic signature (RS) and International Prognostic Index (IPI) to predict the progression-free survival (PFS) and overall survival (OS) of patients with diffuse large B-cell lymphoma (DLBCL). Methods We retrospectively enrolled 152 DLBCL patients and divided them into a training cohort (n = 100) and a validation cohort (n = 52). A total of 1245 radiomic features were extracted from the total metabolic tumor volume (TMTV) and the metabolic bulk volume (MBV) of pre-treatment PET/CT images. The least absolute shrinkage and selection operator (LASSO) algorithm was applied to develop the RS. Cox regression analysis was used to construct hybrid nomograms based on different RS and clinical variables. The performances of hybrid nomograms were evaluated using the time-dependent receiver operator characteristic (ROC) curve and the Hosmer–Lemeshow test. The clinical utilities of prediction nomograms were determined via decision curve analysis. The predictive efficiency of different RS, clinical variables, and hybrid nomograms was compared. Results The RS and IPI were identified as independent predictors of PFS and OS, and were selected to construct hybrid nomograms. Both TMTV- and MBV-based hybrid nomograms had significantly higher values of area under the curve (AUC) than IPI in training and validation cohorts (all P P > 0.05). The Hosmer–Lemeshow test showed that both TMTV- and MBV-based hybrid nomograms calibrated well in the training and validation cohorts (all P > 0.05). Decision curve analysis indicated that hybrid nomograms had higher net benefits than IPI. Conclusion The hybrid nomograms combining RS with IPI could significantly improve survival prediction in DLBCL. Radiomic analysis on MBV may serve as a potential approach for prognosis assessment in DLBCL. Trial registration NCT04317313. Registered March 16, 2020. Public site: https://clinicaltrials.gov/ct2/show/NCT04317313

Fine-grained image recognition is an important task in the field of computer vision. In fine-grained image recognition, the difference between different categories is very small. Thus, fine-grained image recognition highly depends on local features. In this paper, a novel “Attention Cutting And Padding Learning” method is proposed to learn the local features. Firstly, the image is fed to Convolutional Neural Networks, and a saliency map is gotten. According to the saliency map, the attention image is obtained. Secondly, the attention image is cut into $$N*N$$ sub-images. Every sub-image is padded by 0 and the padding size is P. All sub-images are spliced into a Cutting And Padding image. Finally, the Cutting And Padding image and the attention image are fed to CNNs to train. In this method, more local features can be learned, and the high-level semantics is not damaged. Experimental results show that the recognition accuracy of Attention Cutting And Padding Learning is 87.9%, 94.6%, and 92.4% respectively on CUB-200-2011, Stanford Cars, and FGVC-Aircraft dataset. Moreover, this method can be easily applied to biodiversity automatic monitoring, intelligent retail, intelligent transportation, and other fields to improve recognition accuracy without changing the network structure.

Mobile English learning has multiple advantages and brings enormous benefits to EFL learners. However, not everyone adopts it, and the determinants of learners’ adoption intention have not yet been investigated fully. This study aimed to better understand learners’ adoption by employing the theory of planned behaviour (TPB) in conjunction with the influences of technostress and compatibility. Based on existing literature, a research model was proposed and verified with a sample of 409 undergraduates from a Chinese university. The results indicated that in the context of mobile English learning: (a) Individuals with higher adoption intention are more likely to engage in mobile English learning with higher frequency (b = 0.473, P < 0.001) and longer duration (b = 0.330, P < 0.001); (b) Individuals’ attitude toward mobile English learning (b = 0.171, P < 0.05), perceived behavioural control (b = 0.221, P < 0.001), subjective norms (b = 0.237, P < 0.05), and compatibility (b = 0.443, P < 0.001) are significantly positively associated with their adoption intention; (c) Compatibility is the strongest predictor of adoption intention (b = 0.443, P < 0.001) and negatively moderates the effect of subjective norms on adoption intention (b = –0.103, P < 0.005); (d) The influence of technostress on the adoption intention of mobile English learning is not significant (b = –0.041, P > 0.05). Practical implications related to mobile English learning were discussed.

Multiplications have been commonly conducted in quantized CNNs, filters, and reconfigurable cores, and so on, which are widely deployed in mobile and embedded applications. Most multipliers are designed to perform multiplications with symmetric bit-widths, i.e., n - by n -bit multiplication. Such features would cause extra area overhead and performance loss when m - by n -bit multiplications ( m > n ) are deployed in the same hardware design, resulting in inefficient multiplication operations. It is highly desired and challenging to propose a reconfigurable multiplier design to accommodate operands with both symmetric and asymmetric bit-widths. In this work, we propose a reconfigurable approximate multiplier to support multiplications at various precisions, i.e., bit-widths. Unlike prior works of approximate adders assuming a uniform weight distribution with bit-wise independence, scenarios like a quantized CNN may have a centralized weight distribution and hence follow a Gaussian-like distribution with correlated adjacent bits. Thus, a new block-based approximate adder is also proposed as part of the multiplier to ensure energy-efficient operation with an awareness of the bit-wise correlation. Our experimental results show that the proposed approximate adder significantly reduces the error rate by 76% to 98% over a state-of-the-art approximate adder for Gaussian-like distribution scenarios. Evaluation results show that the proposed multiplier is 19% faster and 22% more power saving than a Xilinx multiplier IP at the same bit precision and achieves a 23.94-dB peak signal-to-noise ratio, which is comparable to the accurate one of 24.10 dB when deployed in a Gaussian filter for image processing tasks.

Objective. It has been demonstrated that schizophrenia (SZ) is characterized by functional dysconnectivity involving extensive brain networks. However, the majority of previous studies utilizing resting-state functional magnetic resonance imaging (fMRI) to infer abnormal functional connectivity (FC) in patients with SZ have focused on the linear correlation that one brain region may influence another, ignoring the inherently nonlinear properties of fMRI signals. Approach. In this paper, we present a neural Granger causality (NGC) technique for examining the changes in SZ’s nonlinear causal couplings. We develop static and dynamic NGC-based analyses of large-scale brain networks at several network levels, estimating complicated temporal and causal relationships in SZ patients. Main results. We find that the NGC-based FC matrices can detect large and significant differences between the SZ and healthy control groups at both the regional and subnetwork scales. These differences are persistent and significantly overlapped at various network sparsities regardless of whether the brain networks were built using static or dynamic techniques. In addition, compared to controls, patients with SZ exhibited extensive NGC confusion patterns throughout the entire brain. Significance. These findings imply that the NGC-based FCs may be a useful method for quantifying the abnormalities in the causal influences of patients with SZ, hence shedding fresh light on the pathophysiology of this disorder.

Purpose Epilepsy is one of the most disabling neurological disorders, which affects all age groups and often results in severe consequences. Since misdiagnoses are common, many pediatric patients fail to receive the correct treatment. Recently, 18F-fluorodeoxyglucose positron emission tomography (18F-FDG PET) imaging has been used for the evaluation of pediatric epilepsy. However, the epileptic focus is very difficult to be identified by visual assessment since it may present either hypo- or hyper-metabolic abnormality with unclear boundary. This study aimed to develop a novel symmetricity-driven deep learning framework of PET imaging for the identification of epileptic foci in pediatric patients with temporal lobe epilepsy (TLE). Methods We retrospectively included 201 pediatric patients with TLE and 24 age-matched controls who underwent 18F-FDG PET-CT studies. 18F-FDG PET images were quantitatively investigated using 386 symmetricity features, and a pair-of-cube (PoC)-based Siamese convolutional neural network (CNN) was proposed for precise localization of epileptic focus, and then metabolic abnormality level of the predicted focus was calculated automatically by asymmetric index (AI). Performances of the proposed framework were compared with visual assessment, statistical parametric mapping (SPM) software, and Jensen-Shannon divergence-based logistic regression (JS-LR) analysis. Results The proposed deep learning framework could detect the epileptic foci accurately with the dice coefficient of 0.51, which was significantly higher than that of SPM (0.24, P < 0.01) and significantly (or marginally) higher than that of visual assessment (0.31–0.44, P = 0.005–0.27). The area under the curve (AUC) of the PoC classification was higher than that of the JS-LR (0.93 vs. 0.72). The metabolic level detection accuracy of the proposed method was significantly higher than that of visual assessment blinded or unblinded to clinical information (90% vs. 56% or 68%, P < 0.01). Conclusion The proposed deep learning framework for 18F-FDG PET imaging could identify epileptic foci accurately and efficiently, which might be applied as a computer-assisted approach for the future diagnosis of epilepsy patients. Trial registration NCT04169581. Registered November 13, 2019 Public site: https://clinicaltrials.gov/ct2/show/NCT04169581

18F-fluorodeoxyglucose (18F-FDG) Positron Emission Tomography (PET) imaging usually needs a full-dose radioactive tracer to obtain satisfactory diagnostic results, which raises concerns about the potential health risks of radiation exposure, especially for pediatric patients. Reconstructing the low-dose PET (L-PET) images to the high-quality full-dose PET (F-PET) ones is an effective way that both reduces the radiation exposure and remains diagnostic accuracy. In this paper, we propose a resource-efficient deep learning framework for L-PET reconstruction and analysis, referred to as transGAN-SDAM, to generate F-PET from corresponding L-PET, and quantify the standard uptake value ratios (SUVRs) of these generated F-PET at whole brain. The transGAN-SDAM consists of two modules: a transformer-encoded Generative Adversarial Network (transGAN) and a Spatial Deformable Aggregation Module (SDAM). The transGAN generates higher quality F-PET images, and then the SDAM integrates the spatial information of a sequence of generated F-PET slices to synthesize whole-brain F-PET images. Experimental results demonstrate the superiority and rationality of our approach.

The recent technology advancement on unmanned aerial vehicle (UAV) has enabled diverse applications in vision-related outdoor tasks. Visual object detection is a crucial task among them. However, it is difficult to actually deploy detectors on embedded devices due to the challenges among energy consumption, accuracy, and speed. In this article, we address a few key challenges from the platform, application to the system, and propose an energy-efficient system for real-time UAV object detection on an embedded platform. The proposed system can achieve speed of 28.5 FPS and 2.7-FPS/W energy efficiency on the data set from 2018 low-power object detection challenges (LPODCs).

Weakly supervised object localization is a basic research in the field of computer vision. In this paper, a hierarchical saliency mapping network for object localization is proposed and designed to avoid missing detailed information of potential object. Based on the classical convolution network, we remove the fully connected part and add multiple information extraction branches. The network extracts information from convolution layers of different scales to generate Hierarchical Saliency Map. Hierarchical Saliency Maps that include Hierarchical-Class Activation Map and Hierarchical-Spatial Pyramid Saliency Map fuse deep-level features and low-level features to locate object. The datasets used for testing are Caltech-UCSD Birds 200, Caltech101 and ImageNet. Compared with Class Activation Map and Spatial Pyramid Saliency Map, the localization accuracy has been improved. This method can be used for fine-grained classification, object tracking and other fields.

Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well-known for their bursty workloads and limited energy storage—usually in the form of tiny batteries. To ensure battery lifetime, dynamic voltage frequency scaling (DVFS) has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, induces large ${\text {L}di}{/}{\mathrm {d}t}$ noise, thereby stressing the power delivery system (PDS). Due to the limited area and cost target, adding additional decoupling capacitance to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase/decrease the clock frequency in steps, also known as, clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this paper, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The experiments show that the optimized sequence is able to significantly mitigate noise within the desired transition time, thereby saving both power and energy.

Recent years have witnessed remarkable success of deep learning methods in quality enhancement for compressed video. To better explore temporal information, existing methods usually estimate optical flow for temporal motion compensation. However, since compressed video could be seriously distorted by various compression artifacts, the estimated optical flow tends to be inaccurate and unreliable, thereby resulting in ineffective quality enhancement. In addition, optical flow estimation for consecutive frames is generally conducted in a pairwise manner, which is computational expensive and inefficient. In this paper, we propose a fast yet effective method for compressed video quality enhancement by incorporating a novel Spatio-Temporal Deformable Fusion (STDF) scheme to aggregate temporal information. Specifically, the proposed STDF takes a target frame along with its neighboring reference frames as input to jointly predict an offset field to deform the spatio-temporal sampling positions of convolution. As a result, complementary information from both target and reference frames can be fused within a single Spatio-Temporal Deformable Convolution (STDC) operation. Extensive experiments show that our method achieves the state-of-the-art performance of compressed video quality enhancement in terms of both accuracy and efficiency.

LC resonant clock is a viable option for low power on-chip clock distributions. A major limiting factor to its implementation is the large area overhead due to the use of conventional spiral inductors. On the other hand, idle through-silicon-vias (TSVs) in 3-D integrated circuits (3-D ICs) can form vertical inductors with minimal footprint and have little noise coupling with horizontal traces, particularly suitable for the application of LC resonant clock. However, due to the strict constraints on the location of idle TSVs, the use of the TSV inductor is constrained by its location, inductance, and quality factor. The problem is further complicated by dynamic frequency scaling (DFS), where the resonant tanks need to accommodate multiple clock frequencies. Moreover, these TSV inductors can be in any orientation with any distance apart, thereby causing complicated coupling effects. In this paper, we first present a novel scheme to opportunistically use idle TSVs to form inductors in LC resonant clock of 3-D ICs for maximum power reduction in clock-distribution network (CDN) at a fixed frequency, and then extend it to DFS schemes. Experimental results on a few industrial designs for the resonant CDNs operated at a fixed frequency of 3 GHz show that the power consumption is reduced by up to 47.9% compared with the conventional CDNs without resonant clocking. In addition, for the resonant CDNs with DFS scheme, the power consumption reduced by up to 42.3%, 39.0%, 38.3%, 34.3%, and 28.6% at 3, 2.5, 2, 1.5, and 1 GHz frequency, respectively, compared with the CDNs without resonant clocking. When compared with CDNs with conventional spiral inductors, our scheme with TSV inductors can reduce the inductor footprint by up to $6.30 \times$ with the same power consumption.

The switched-capacitor converter (SCC) has been widely used for voltage regulation in multicore chips, where energy efficiency is the major concern. However as the overhead to integrate SCCs in a chip is non-negligible, the SCCs could not be overused. Hence in this paper we propose an early stage SCCs planning framework to obtain the SCC supply scheme together with the optimized Metal-Insulator-Metal (MIM) capacitance allocation and converter ratio selection for each SCC when the given number of SCCs is less than the number of cores . Besides, our method could also explore to find the best number of used SCCs for a given chip. The experiments show the results of our SCC planning methods.

The electronic, optical, and magnetic properties of graphene nanoribbons (GNRs) can be engineered by controlling their edge structure and width with atomic precision through bottom-up fabrication based on molecular precursors. This approach offers a unique platform for all-carbon electronic devices but requires careful optimization of the growth conditions to match structural requirements for successful device integration, with GNR length being the most critical parameter. In this work, the growth, characterization, and device integration of 5-atom wide armchair GNRs (5-AGNRs) are studied, which are expected to have an optimal bandgap as active material in switching devices. 5-AGNRs are obtained via on-surface synthesis under ultrahigh vacuum conditions from Br- and I-substituted precursors. It is shown that the use of I-substituted precursors and the optimization of the initial precursor coverage quintupled the average 5-AGNR length. This significant length increase allowed the integration of 5-AGNRs into devices and the realization of the first field-effect transistor based on narrow bandgap AGNRs that shows switching behavior at room temperature. The study highlights that the optimized growth protocols can successfully bridge between the sub-nanometer scale, where atomic precision is needed to control the electronic properties, and the scale of tens of nanometers relevant for successful device integration of GNRs.

In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages. Although this fully synchronous style can reduce design efforts significantly, it may affect circuit performance negatively, because sequential components can only introduce delays into signal propagations but never accelerate them. In this paper, we propose a new timing model, VirtualSync+, in which signals, specially those along critical paths, are allowed to propagate through several sequential stages without flip-flops. Timing constraints are still satisfied at the boundary of the optimized circuit to maintain a consistent interface with existing designs. By removing clock-to-q delays and setup time requirements of flip-flops on critical paths, the performance of a circuit can be pushed even beyond the limit of traditional sequential designs. In addition, we further enhance the optimization with VirtualSync+ by fine-tuning with commercial design tools, e.g., Design Compiler from Synopsys, to achieve more accurate result. Experimental results demonstrate that circuit performance can be improved by up to 4% (average 1.5%) compared with that after extreme retiming and sizing, while the increase of area is still negligible. This timing performance is enhanced beyond the limit of traditional sequential designs. It also demonstrates that compared with those after retiming and sizing, the circuits with VirtualSync+ can achieve better timing performance under the same area cost or smaller area cost under the same clock period, respectively.

Cache plays an important role to maintain high and stable performance (i.e. high throughput, low tail latency and throughput jitter) in storage systems. Existing rule-based cache management methods, coupled with engineers' manual configurations, cannot meet ever-growing requirements of both time-varying workloads and complex storage systems, leading to frequent cache overloading. In this paper, we for the first time propose a light-weight learning-based cache bandwidth control technique, called \LQoCo which can adaptively control the cache bandwidth so as to effectively prevent cache overloading in storage systems. Extensive experiments with various workloads on real systems show that LQoCo, with its strong adaptability and fast learning ability, can adapt to various workloads to effectively control cache bandwidth, thereby significantly improving the storage performance (e.g. increasing the throughput by 10\%-20\% and reducing the throughput jitter and tail latency by 2X-6X and 1.5X-4X, respectively, compared with two representative rule-based methods)., Comment: This paper has been accepted by DAC 2022. Xijun is the correspoonding author