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Extension doping for FinFETs is more difficult compared with planar devices due to fin geometry. An amorphization problem for NMOS FinFETs and photo resist shadowing for CMOS FinFETs are pointed out when standard ion implantation (I/I) is used. Amorphization of the fin results in poor recrystallization during subsequent annealing. The whole fin can easily be amorphized when As is implanted at high dose to form source and drain extensions, especially for narrow FinFETs. Fin sputter erosion can be seen when narrow tilt angle standard As I/I is employed. These are serious concerns because they degrade the device performance and increase the variability. In this study, the improvement of the fin amorphization and the fin sputter erosion of standard I/I is reported. The optimization procedure and the optimized result of standard I/I are discussed. In addition, the difference between the device performance for 7 degrees tilt As I/I and the optimized 30 degrees tilt As I/I, which is almost -conformal doping, has been quantified.

The objective of this work is to study the effect of pMOSFETs lightly doped drain (p+LDD) using two different species of dopants; boron and boron di-flouride using TCAD Simulation. The result from this simulation was compared with electrical measurements on silicon wafers. In our experiments, we used the same dose for both of the dopants, at dose A. We only systematically split the energy for BF2 into three splits. 2D simulation results using TSUPREM-4 and MEDICI help us to understand the mechanism involved. Our results show improvement for the junction profile by comparing BF2 and boron. It has been reported before, that incorporating fluorine from BF2 dopant is very useful for the shallow junction devices (J.R. Pfiester et al., 1990). This beneficial effect of a BF2 p+LDD will make improvement on the device performance. Since the experiment is comparing the simulation data with the experimental data, it will be very useful for the process engineer to tune their process implant parameters for a future technology.

In this paper we investigate the mechanism of local mechanical stress reduction in CMOS transistors by improving the Inter Layer Dielectric (ILD) process. We changed the Etch Stop Liner (ESL) from single stack silicon nitride (SiN) to dual stack ESL SiN/SiON similar to [1]. We then simulate the stress in 2-D for both n- and p- channel MOSFET, and investigate how an oxynitride (SiON) buffer layer under the SiN ESL can reduce the longitudinal (X) and the lateral (Y) stress in both n- and p- channel thus improving the overall CMOS performance. Our result shows that the dual SiN/SiON layer reduces the stress in the channel length direction (Sxx), perpendicular to channel plane direction (Syy) and channel width direction (Szz). It is known that decreasing the compressive stress in the X direction improves NMOS but degrades PMOS. Our experimental data shows that the additional SiON layer reduces the stress in the channel, hence increases the electron mobility.