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This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts a PCIe Gen four-host interface for higher data throughput. It is implemented with dual bi-directional transceiver architecture and signal retiming scheme to maximize the valid data window opening on solid-state drive (SSD) channels. Also, it facilitates training between F-chip and NAND using an on-chip delay-locked loop whose locking is proposed in strobe-based NAND systems to achieve sufficient signal integrity (SI) of the in-package channel at a speed of 1.8 Gb/s/pin. Embedded built-in self-test evaluates un-selected paths and determines if re-training is required without losing data throughput performance. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND technology requires addressing several common issues: 1) As the number of WL stack layers increases, the cell-string current is reduced due to the increased resistance in a cell string, 2) Deterioration of cell-to-cell interference, due to the reduction of cell pitch, 3) Support of higher IO bandwidth for faster data transfer speed [1]. Another challenge of this work was to minimize the die size because the peripheral circuit area is comparable to that of the cell array. Hence, we integrated the peripheral circuits below the cell array as introduced in [2]. Also, to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area.

In this paper, design challenges and key technologies to overcome the hurdles for the future 3D NAND are introduced. More specifically, state-of-the-art solutions for higher density, lower cost and higher bandwidth NAND is covered in detail.

A 1.2 V, 1.8 Gb/s/pin 16Tb-NAND flash memory multi-chip package incorporating with 16-dies of 1-Tb NAND flash memory and the 3rd generation F-Chip is proposed. The proposed F-Chip is developed to meet the performance requirements of high capacity storage devices that adopts PCIe Gen 4 host interface for faster data throughput. It is implemented with Toggle 4.0 standard on dual bi-directional transceiver architecture to achieve maximum valid data window on SSD channels. Also, it facilitates training between F-chip and NAND using on chip DLL and BIST to achieve sufficient signal integrity on in-package channel for 1.8Gb/s/pin. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

A full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor architectures, RAMP and DigiAcc, are proposed based on the analysis, and a prototype development platform (REMY) is implemented. REMY includes a software graphics library and simulation environment developed for more flexible realization of mobile 3D graphics. The experimental results demonstrate the feasibility of mobile 3D graphics with 3.6 Mpolygons/s at 155 mW power consumption for full 3D operation.

Lactic acid bacteria were isolated from silage, which produce high level of hydrogen peroxide in cell culture supernatant. The 16S rDNA sequences of the isolate matched perfectly with that of Lactobacillus fermentum (99.9%), examined by a 16S rDNA gene sequence analysis and similarity search using the GenBank database, thus named L. fermentum CS12-1. L. fermentum CS12-1 showed resistance to low pH and bile acid. The production of hydrogen peroxide by L. fermentum CS12-1 was confirmed by catalase treatment and high-performance liquid chromatography. L. fermentum CS12-1 accumulated hydrogen peroxide in culture broth as cells grew, and the highest concentration of hydrogen peroxide reached 3.5 mM at the late stationary growth phase. The cell-free supernatant of L. fermentum CS12-1 both before and after neutralization inhibited the growth of enterotoxigenic Escherichia coli K88 that causes diarrhea in piglets. (Asian-Aust. J. Anim. Sci. 2005. Vol 18, No. 1 : 90-95)

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-/spl mu/m pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur.

A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-/spl mu/m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW.

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated.

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

In this paper, first, it has been discussed hot carrier reliability in both Pch, RCAT and SRCAT. Second, we showed the origin of electric field suppression where the supply-voltage is applied at the same bias condition. Furthermore, we discuss the effects of ion implant process

We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using a top-down design approach. A pipeline structure in the row path and integration of multiple SRAM buffers enable fast row-cycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with a conventional SDRAM interface and consumes low power by adopting partial cell core activation.

We propose a Synchronous Pipelined DRAM (SP-DRAM) architecture which has a fast row-cycle. Pipeline circuitry is inserted in the row path and multiple SRAM buffers are integrated in the DRAM to reduce row latency. The data transfer rate of the SP-DRAM is measured to be faster by 40% than SDRAM and by 20% than VCM as a result of system level performance analysis. A partial activation scheme is adopted in the cell core to reduce unnecessary power consumption. The SP-DRAM can maintain compatibility with a conventional SDRAM interface with negligible performance degradation.

We propose POPeye that can measure and analyze the performance of the DRAM in real PC environment. POPeye is composed of a virtual PC and hardware structural simulator. Virtual PC of POPeye emulates the total PC system on Unix environment. While running real applications such as Windows95 and MS-office, POPeye's hardware structural simulator can offer the detailed information of transactions between CPU and memory system.

An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.

We implemented POPeye (Probe of Performance+eye), a system analysis simulator to evaluate DRAM performance in a personal computer environment. When running any real-life application programs such as Microsoft Office and Paint Shop Pro on Windows OS, POPeye simulates detailed transactions between a CPU and a memory system. Using this tool, we comparatively analyzed the performance of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM.

A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.