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Data centers are increasingly using high-speed circuit switches to cope with the growing demand and reduce operational costs. One of the fundamental tasks of circuit switches is to compute a sparse collection of switching configurations to support a traffic demand matrix. Such a problem has been addressed in the literature with variations of the approach proposed by Birkhoff in 1946 to decompose a doubly stochastic matrix exactly. However, the existing methods are heuristic and do not have theoretical guarantees on how well a collection of switching configurations (i.e., permutations) can approximate a traffic matrix (i.e., a scaled doubly stochastic matrix). In this paper, we revisit Birkhoff’s approach and make three contributions. First, we establish the first theoretical bound on the sparsity of Birkhoff’s algorithm (i.e., the number of switching configurations necessary to approximate a traffic matrix). In particular, we show that by using a subset of the admissible permutation matrices, Birkhoff’s algorithm obtains an ǫ-approximate decomposition with at most O(log(1/ǫ)) permutations. Second, we propose a new algorithm, Birkhoff+, which combines the wealth of Frank-Wolfe with Birkhoff’s approach to obtain sparse decompositions in a fast manner. And third, we evaluate the performance of the proposed algorithm numerically and study how this affects the performance of a circuit switch. Our results show that Birkhoff+ is superior to previous algorithms in terms of throughput, running time, and number of switching configurations.

A hybrid optical/electrical datacenter network (HOE-DCN) integrates the benefits of electrical packet switching (EPS) and optical circuit switching (OCS) for better architectural scalability. Meanwhile, as each network service usually involves multiple virtual machines (VMs) that form a virtual network (VNT), how to reconfigure the VNTs in an HOE-DCN to adapt to the dynamic network environment becomes an interesting and important problem to tackle. In this work, we optimize the procedure of VNT reconfigurations that remap VNTs to given virtual network embedding (VNE) schemes, i.e. , scheduling the required VM migrations and optical cross-connect (OXC) reconfiguration properly such that the overall VNT reconfiguration latency can be minimized. We first assume that all the VM migrations should be scheduled before the OXC reconfiguration to minimize service interruptions, and formulate a mixed integer linear programming (MILP) model to solve the scheduling problem exactly. Then, with the same assumption, we propose a time-efficient heuristic to schedule parallel VM migrations in batches such that the bandwidth competition can be significantly relieved. Finally, we divide the OXC reconfiguration into several progressive steps, and design a joint scheduling algorithm to arrange VM migrations together with the OXC reconfiguration steps.

Discrete-time queueing systems have widespread applications in packet switching networks, internet protocol, Broadband Integrated Services Digital Network (B-ISDN), circuit switched time-division m...

In this paper, it is considered the broadband backbone optical networks with wavelength routing and circuit switching used to build long-range wide area networks. In this type of network, if there is an available and acknowledged connection request, it is necessary to determine the optimal path between the optical communication nodes in the network. This also requires the assignment of an optimal set of wavelengths along the selected route between these nodes. This paper takes into account the multichannel optical communication networks with spectral multiplexing. Four different routing algorithms are modeled and analyzed for which their weight functions are determined to take into account various factors, such as the total distance of the individual routes, the total number of available wavelengths for a given route and how many of them are available for use. It is studied and compared the performance of the proposed algorithms in a multichannel optical network in terms of blocking probability.

Nowadays, optical circuit switching is becoming an increasingly favored technology in scaling data center networks for its definitive advantages in data rate, power consumption, and device cost. Concurrently, reducing coflow completion time (CCT) is of great significance for improving application-level performance. However, minimizing CCT in circuit switched networks is totally different from that in traditional packet switched networks due to port constraints and circuit reconfiguration delays. To address this issue, this article proposes Grouped Optimization-based Scheduling (GOS), a CCT minimization algorithm for circuit switched networks integrating circuit and coflow scheduling. We first formalize the CCT minimization problem into a 0-1 programming problem, then relax and solve the problem in 2 steps to obtain the coflow order and flow grouping decisions on each circuit. Thus intra-group reconfiguration delays are saved, and small coflows can be prioritized at the group level. Theoretical analysis proves GOS is a 4-approximation algorithm in average CCT. To reduce computing overheads, we further propose a heuristic approximation algorithm. Extensive simulations show that the heuristic algorithm has satisfactory CCT performance (0.12× Varys, 0.36× Sunflow) as well as high throughput (16.74× Varys, 1.32× Sunflow), and well adapts to a wide range of reconfiguration delays and algorithm decision time.

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

Novel approaches to switching ultra-fast semiconductor optical amplifiers using artificial intelligence algorithms (particle swarm optimisation, ant colony optimisation, and a genetic algorithm) are developed and applied both in simulation and experiment. Effective off-on switching (settling) times of 542 ps are demonstrated with just 4.8% overshoot, achieving an order of magnitude improvement over previous attempts described in the literature and standard dampening techniques from control theory., This manuscript was accepted for publication in the IEEE/OSA Journal of Lightwave Technology on 21st June 2020. Open access code: https://github.com/cwfparsonson/soa_driving Open access data: https://doi.org/10.5522/04/12356696.v1

Photonic network-on-chip is utilized as a candidate paradigm for important attributes such as high bandwidth and low energy consumption. In this paper, a non-blocking five-port photonic router is proposed for the 2-D mesh topology, which is called Surix. Surix has been designed for improving the physical layer and the network’s performance parameters in multi-core network topologies. Moreover, a new routing algorithm on Surix is proposed, in which turning models and the circuit switching method are used for mitigating photonic insertion loss and power consumption of the photonic layer. The proposed algorithm can select various source and destination nodes through the selected routes with the lowest insertion loss and power consumption. The simulation results show that Surix outperforms conventional routers in network performance parameters. For instance, the insertion loss of Surix in the mesh topology shows a 9.92–37.15 percent improvement compared to conventional routers.

This paper presents an experimental research on configuration optimization of a frost-free refrigerator-freezer with the parallel circuit cycle based on the analysis of circuit switching characteristics. Through combination optimization of R-fan voltage, F-fan voltage, R-capillary tube flow capacity, refrigerant charge, structure of suction pipe, F-compressor speed and R-compressor speed, the system could save 9.27% energy consumption compared with the initial condition. The experimental results also showed that the larger the R-capillary tube flow capacity, the larger the flow rate of the RC, resulting in the quickly temperature drop in R-cabinet and slowly temperature drop in R-cabinet based on “R-cabinet temperature priority” control strategy. Additionally, the R-cabinet temperature drop rate decreased with the increase of ambient temperature but the F-cabinet temperature drop rate was almost unaffected by the ambient temperature.

We introduce PULSE, a sub-microsecond optical circuit-switched data centre network architecture controlled by distributed hardware schedulers. PULSE is a flat architecture that uses parallel passive coupler-based broadcast and select networks. We employ a novel transceiver architecture, for dynamic wavelength-timeslot selection, to achieve a reconfiguration time down to O(100ps), establishing timeslots of O(10ns). A novel scheduling algorithm that has a clock period of 2.3ns performs multiple iterations to maximize throughput, wavelength usage and reduce latency, enhancing the overall performance. In order to scale, the single-hop PULSE architecture uses sub-networks that are disjoint by using multiple transceivers for each node in 64 node racks. At the reconfiguration circuit duration (epoch = 120 ns), the scheduling algorithm is shown to achieve up to 93% throughput and 100% wavelength usage of 64 wavelengths, incurring an average latency that ranges from 0.7-1.2 microseconds with best-case 0.4 microsecond median and 5 microsecond tail latency, limited by the timeslot (20 ns) and epoch size (120 ns). We show how the 4096-node PULSE architecture allows up to 260k optical channels to be re-used across sub-networks achieving a capacity of 25.6 Pbps with an energy consumption of 85 pJ/bit., 16 pages, 12 figures

This article discusses a DC–DC converter based solar fed PV array system for low power applications. A single diode based solar panel is designed and modelled for this PV array system. At low value of irradiance in solar panel, the system will perform with better accuracy. To acquire better efficiency, the similar system is operated with Maximum Power Point Tracking (MPPT) control algorithm. The solar panel current v/s Voltage (I–V) and Power v/s Voltage (P–V) characteristics curves are obtained from Matlab simulation. The comparison of simulation curves is also done with the curves obtained from the experiment results. The detailed investigation of DC–DC converters with solar fed system with soft-switching technique is also performed. This soft-switching technique is formed by using the resonant inductors and capacitors. These passive components reduce the circuit switching losses. The Zero Voltage Switching (ZVS) technique is used to eliminate the switching losses developed in the circuit at the time of switching transitions. This technique also reduces the dv/dt noise owing to junction capacity discharge. This Proposed ZETA and SEPIC converters based system are modelled and simulated in MATLAB program and its performance is evaluated through experimentation in the terms of losses and efficiency. From the performance study of ZVS ZETA and SEPIC converter, increment in efficiency are obtained 1.97% and 7.23% under Perturb and Observe MPPT control and 4.14% and 0.41% in Incremental Conductance MPPT control respectively as compared to its conventional ZETA and SEPIC converter.

As data centers enter the exascale computing era, the traffic exchanged between internal network nodes, increases exponentially. Optical networking is an attractive solution to deliver the high capacity, low latency, and scalable interconnection needed. Among other switching methods, packet switching is particularly interesting as it can be widely deployed in the network to handle rapidly-changing traffic of arbitrary size. Nanosecond-reconfigurable photonic integrated switch fabrics, built as multi-stage architectures such as the Clos network, are key enablers to scalable packet switching. However, the accompanying control plane needs to also operate on packet timescales. Designing a central scheduler, to control an optical packet switch in nanoseconds, presents a challenge especially as the switch size increases. To this end, we present a highly-parallel, modular scheduler design for Clos switches along with a proposed routing scheme to enable nanosecond scalable scheduling. We synthesize our scheduler as an application-specific integrated circuit (ASIC) and demonstrate scaling to a 256 × 256 size with an ultra-low scheduling delay of only 6.0 ns. In a cycle-accurate rack-scale network emulation, for this switch size, we show a minimum end-to-end latency of 30.8 ns and maintain nanosecond average latency up to 80% of input traffic load. We achieve zero packet loss and short-tailed packet latency distributions for all traffic loads and switch sizes. Our work is compared to state-of-the-art optical switches, in terms of scheduling delay, packet latency, and switch throughput.

In this paper, a general description of the problem of calculating probability–time characteristics was presented. At the initial stage of studying this problem, we studied the asynchronous data transmission of the constituent broadband digital network with the integration of services for both the channel switching subnetwork and the packet switching subnetwork. And also the circuit switching subnetwork was investigated using the bypass of the direction of transmission of the stream of multi-channel calls. At the same time, the source data of the problem of calculating probabilistic characteristics were set for the channel switching subnetwork, the characteristics that were determined during the solution of the problem were listed, and some assumptions were described that made it possible to adequately approximate the study of such a model to the functioning of a real network. Next, a mathematical model for calculating the loss probabilities was described, both for communication channels and for nodes of the channel switching subnetwork included in the asynchronous transfer mode network. The model of information traffic transmission is presented, where the method is implemented using network bypass directions. A method has been developed for generating a nodal load of a channel switching subnet and a system of equations has been obtained, the solution of which determines the value of a nodal load relative to the probability of loss on communication channels and proved the uniqueness of the solution of this system of equations.

Fast optical circuit switching has significant potential to solve scaling issues with traditional packet-switch-based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. Here we present a system-level integration of a nanosecond-scale $2\times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

In handover procedure, target cell would be prepared and UE will move on target cell based on the configuration sent by source eNodeB to User Equipment. Cell Reselection happens only when the user equipment (or Mobile Phone) is in Idle MODE, and the User Equipment needs to go a more appropriate cell. The main feature of CSFB Ps handover does not interrupt data transfer when switching from Long Term Evolution to UTRAN/GSM. After switching to 3G is already in connected mode it does not waste time to switch to connected mode. This feature let us improve call setup time when we make call in LTE.

All-optical circuit switched network core is the holy grail for the next-generation datacenter architectures, as electrical packet switches are struggling to cope up with increasing challenges posed by the end of Moore's law. However, traffic skewness is the biggest enemy of such all-optical network cores comprising of a simple round-robin circuit-scheduling abstraction. Even though valiant load balancing can theoretically solve the problem, it falls short in most of the practical scenarios. In this paper, we point towards a new research direction to address the skewness problem: why not resolve most of the skewness at the network edge while keeping the optical core simple? This approach is fundamentally different and can potentially enable the all-optical network core to achieve good performance in practice. We discuss relevant strategies and envision that a holistic system design is necessary considering all these strategies together.

The paper considers methods of realization of relaysemiconductor circuit switching in systems of railway automatics with the use of promising elemental base. It also gives recommendations on selection of semiconductor switching elements for various spheres of application of relay interface units.

The ever-increasing communication requirements have led to the introduction of optical circuit switch (OCS) to data center, which is capable of providing more flexible bandwidth allocation compared to the electrical packet switching. However, the challenge still arises due to non-negligible reconfiguration delay of commercially available MEMS-based optical circuit switching technology, even though it provides high bandwidth with low per-bit cost and power. Additionally, existing scheduling schemes amortize long switch delay by means of reconfiguring OCS every a few 100 s of milliseconds, not only causing the degradation of the latency performance, but also incurring the low utilization of optical links. In this paper, we propose an OCS-based scheduling scheme called relay-based schedule scheme (RSS), which can leverage idle optical paths to forward traffic from remote nodes only with straightforward software modifications on controller. We evaluate the performance of the proposed scheme via OMNET++ simulator, and the results demonstrate that our proposal delivers significant benefits, including reducing the average mice flow FCTs (flow complete time) by up to 80% and reducing the end-to-end packet delay by 50% compared to non-RSS schemes.

Quantum-dot cellular automata (QCA) is a nanoscale technology to design digital circuits in nano-measure which acts based on electron’s interaction. The technology of collecting, processing and distributing information is growing rapidly, but the growth in demand for advanced methods in data processing has always been greater than the speed of growth of these technologies. Hence, computer networks play an important role in providing a resource sharing and facilitating user communications. The circuit-switched network is one of the main components for sending input signals between different users within the network. In this paper, a minimal and optimal design of the circuit-switched network is presented at a single level in QCA. The proposed design is studied and compared with existing designs in terms of fault tolerant under stuck-at 0 and 1. There is also a physical analysis for the proposed circuit-switched network.

Purpose. Development of a method for the synthesis of power supply voltage regulator for energy-saving control of asynchronous drives of long-term operation mechanisms with a slightly varying load curve and without the need for speed stabilization. Methodology . For the research, the provisions of the theory of electrical machines, methods of synthesis of automatic systems, mathematical modeling in the MatLab package and methods of statistical analysis were used . Findings. The method was developed and the voltage regulator of energy-saving control of asynchronous drive was synthesized according to its algorithm under the conditions of load oscillation due to the chaotic change of the technological task and ensuring the permissible dynamics due to the intensity setter, which is installed in series with the regulator. Recommendations are given for the sequence and circuit switching on for the automatic system in the start-up and steady-state operation modes, and also the interval of limiting the rational slip value is selected, which will ensure the highest possible energy efficiency. Originality. An original method is proposed for determining the transition function of voltage regulator for energy-saving control of an asynchronous drive with the provision of permissible dynamics in transient conditions and indirect stabilization of the speed of long-term operation mechanisms and with a low-variation load curve. The choice of the interval for limiting the rational slip value and the sequence of switching on the control circuit depending on the current mode of operation of the electric drive system is substantiated. Practical value. The use of the proposed controller will allow the creation of the automatic asynchronous drive system, which can save you up to 47 % of power in case of significant load drop.

This paper proposes and experimentally evaluates a fully developed novel architecture with purpose built low latency communication protocols for next generation disaggregated data centers (DDCs). In order to accommodate for capacity and latency needs of disaggregated IT elements (i.e., CPU, memory), this architecture makes use of a low latency and high-capacity circuit-switched optical network for interconnecting various end points that are equipped with multi-channel silicon photonic based integrated transceivers. In a move to further decrease the perceived latency between various disaggregated IT elements, this paper proposes a novel network topology that cuts down the latency over the optical network by 34% while enhancing system scalability and channel bonding over multi-core fiber (MCF) switched links to reduce head to tail latency and in turn increase sustained memory bandwidth for disaggregated remote memory. Furthermore, to reduce power consumption and enhance space efficiency, the integration of novel MCF-based transceivers, fibers, and optical switches are proposed and experimentally validated at the physical layer for this topology. It is shown that the integration of MCF-based subsystems in this topology can bring about an improvement in energy efficiency of the optical switching layer, which is above 60%. Finally, the performance of this proposed architecture and topology is evaluated experimentally at the application layer where the perceived memory throughput for accessing remote and local resources is measured and compared using electrical circuit and packet switching. The results also highlight a multi-fold increase in application perceived memory throughput over the proposed DDC topology by utilization and bonding of multiple optical channels to interconnect disaggregated IT elements that can be carried over MCF links.

Modular optical switch architectures combining wavelength routing based on arrayed waveguide grating (AWG) devices and multicasting based on star couplers hold promise for flexibly addressing the exponentially growing traffic demands in a cost- and power-efficient fashion. In a default switching scenario, an input port of the AWG is connected to an output port via a single wavelength. This can severely limit the capacity between broadcast domains, resulting in interdomain traffic switching bottlenecks. An unexplored solution to this issue is to exploit multiple AWG free spectral ranges (FSRs), i.e., to set up multiple parallel connections between each pair of broadcast domains. In this paper, we study, for the first time, the influence of the FSR count on the throughput of a multistage switching architecture and propose a generic and novel analytical framework to estimate the blocking probability. We assess the accuracy of our analytical results via Monte Carlo simulations. Our study points to significant improvements with a moderate increase in the number of FSRs. We show that an FSR count beyond four results in diminishing returns. Furthermore, to investigate the tradeoffs between the network- and physical-layer effects, we conduct a cross-layer analysis, taking into account pulse amplitude modulation and rate-adaptive forward error correction. We illustrate how the effective bit rate per port increases with an increase in the number of FSRs.

There are more and more structured traffic flows (a.k.a coflow) in today's data center networks. Completing a coflow is extremely important for various applications, e.g., MapReduce. To reduce the coflow completion time or CCT, one may increase the link capacity by applying advanced optical circuit switches in data center networks. Due to special features of optical circuit switches, both traffic scheduling and circuit scheduling will influence the CCT. However, previous solutions have some significant limitations: they consider either coflow scheduling, or circuit scheduling for only one optical circuit switch, which are both insufficient. In this paper, we study the integrated coflow and circuit scheduling (GCCS) problem with the objective to minimize the CCT, and prove its NP-hardness. We present an integrated algorithm which includes two steps, coflow scheduling and circuit scheduling, respectively. We also analyze that the proposed algorithm can achieve the approximation ratio $O(h)$O(h) in most practical situations, where $h$h is the maximum number of ports among all lightpaths. Through large-scale simulations, we demonstrate that the integrated solution can significantly reduce the CCT by about 43-70 percent compared with the state-of-the-art coflow scheduler for optical networks.

All optical or hybrid electrical/optical switching data center network (DCN) architectures are capable of adapting the optical-layer topology to various network traffic demands based on the flexibility of optical switching technology. The topology reconfiguration strategies in previous research simply attempt to reconfigure optical circuit switching (OCS) links to offload heavier rack-to-rack traffic. However, due to the complex multi-layer interconnections and the various network traffic patterns in DCNs, the OCS links will not only offload the network traffic between its source and destination racks, but also forward the network traffic that belongs to the adjacent racks of the source and destinations racks. Previous strategies ignore the forwarding traffic and result in sub-optimal solutions. In order to overcome the shortcomings of previous methods and make full use of the OCS link resources in DCNs, an effective topology reconfiguration strategy named optical circuit bridge (OCBridge) has been proposed in our recent work. The main idea of our OCBridge is to take into account the traffic demands between the source and destination regions of each OCS link. In this paper, we first review our OCBridge, and then in simulation, we evaluate the performance of our OCBridge by testing it in two typical OCS-based DCNs, including OpenScale and Helios. Under our OCBridge, we analyze the outstanding network throughput performance of the DCNs and investigate the communication distance of traffic demands. Finally, in experiment, we deploy our OCBridge to a small prototype of OpenScale and verify that our OCBridge is capable of accelerating the distributed computing applications compared with previous topology reconfiguration strategies.

Accurate nonlinear parasitic capacitance characterization of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFETs) is essential for device behavior modeling, circuit switching loss optimization and power electronic equipment design. This paper presents an improved characterization method of drain-source capacitance C ds for SiC MOSFET, which combines parasitic capacitance extraction in dynamic switching process and static segmented capacitance characterization. Firstly, an extraction method of parasitic capacitance during dynamic switching transient based on miller plateau is described and it can reflect the real value of C ds in actual electrical conditions, which is essential to the precise modeling and predicting of SiC MOSFET switching performance. Secondly, a segmented characterization method of C ds is proposed to deal with the challenging obstacles on the modeling of nonlinear capacitance outside miller plateau area during switching process. And then, an accurate capacitance modeling method is set up based on these two methods. Finally, the proposed method is verified by establishing a Spice model of SiC MOSFET, and a double pulse test (DPT) experimental platform is built to compare with the simulation results. The comparison results show that the simulation waveform of this proposed method fits better with the experiment one than the previous method, which indicates the high performance of the proposed method.

The paper considers modal reservation (MR) which allows both increasing the circuit reliability and implementing the effect of modal filtering. A quasistatic analysis of the ultrashort pulse propagation was performed in structures with triple MR. It was assumed that the circuit is without failures if the boundary conditions at the ends of the conductors approximately correspond to 50 Ohms, and if one component of the system fails, a 0 or ∞is formed at one of the ends of the circuit. In particular, a triple MR significantly increases the resistance to ultrashort pulses. The optimal switching order was determined for the shielded structure with triple modal reservation. For this structure, a preferable circuit switching option was the one which produced the smallest voltage amplitudes (Umax) of the pulses resulted from the acting ultrashort pulse decomposition. Thus, the choice of this option provides the best protection against ultrashort pulses during the entire operation of the system. As a result switching option 3 is optimal.

We report on a co-planar light-actuated digital microfluidics device that features a metal mesh grid integrated on the device surface to allow droplets to be exposed from above. We discuss a theoretical circuit model for our co-planar optoelectrowetting (OEW) design that allows for the optimization of droplet actuation while maintaining reliable droplet movement. Basic droplet manipulations such as merging and parallel actuation of droplets are achieved at speeds of up to 4.5 cm / s. The co-planar OEW device design benefits from having an open top design that allows for a wider range of system integration configurations than previous generations of OEW devices. A droplet-on-demand dispensing system from above is integrated with the co-planar OEW device to demonstrate the versatility of this optofluidic platform. The ability to inject, collect, and position individual droplets to form large-scale droplet arrays of up to 20 × 20 is achieved.

Temporal encoding has been shown to be a natural fit for single flux quantum (SFQ) superconducting computing since SFQ already encodes information with the presence or absence of voltage pulses. However, past work in SFQ has focused on binary-encoded networks on chip (NoCs). In this paper, we propose superconducting rotary NoC (SRNoC), a NoC where both data and control paths operate in the temporal domain following the race logic (RL) convention. Therefore, SFQ chips with temporal compute or memory can use SRNoC to avoid converting between the temporal and binary domains that would result from using a binary-encoded NoC. Using RL also enables SRNoC to be area-efficient, mitigating SFQ technology’s low device density. SRNoC treats pulses as independent packets and delivers them to outputs without changing their value, i.e. preserving the RL convention. SRNoC operates on a fixed, rotating connection schedule between inputs and outputs. In each connection window, multiple pulses (packets) can be transmitted sequentially. SRNoC provides $13.1\times$ higher throughput per port per Josephson junction (JJ) compared to the best-performing of three demonstrated NoCs.

Advanced flow control mechanisms employed by modern on-chip networks are the reasons of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power and offer an end-to-end latency analogous to wire delay. In this paper, we present a hybrid flow control mechanism, which mixes both virtual channels and circuit-switching, to provide a latency-competitive and energy-efficient on-chip network design. Contrary to existing hybrid switching designs, our proposal is based on local traffic so that circuits are formed without the knowledge of end-to-end traffic. When compared to on-chip networks with virtual channels, our proposal achieves a very competitive latency per flit, for up to 4% lower, while also dramatically suppressing the energy per flit by up to 18%.

A novel service-aware scheduler and optical circuit switch-based system architecture are proposed for disaggregated data centers. The proposed scheduler classifies requested services into four priorities to ensure differentiated bandwidth. The scheduler provides 100% throughput with scheduling time of 63.3 ns. The measured round-trip latency to access disaggregated memory is 1177.6 ns. The optical circuit switch consists of AWGR and tunable wavelength transceivers.

Transport networks are being used to exchange traffic among communication sites. Current transport networks are mostly static, because existing traffic patterns do not fluctuate wildly. However, given that demand fluctuations are likely to become significant due to the emerging diversity of network services, current static networks will have great difficulty in accommodating all future demands. In this paper, we propose a network architecture that can accommodate more demands by employing fiber cross-connects (FXCs) connected with dark fibers; FXCs, e.g., robotic patch panels and micro-electromechanical system, are optical switches that perform circuit-switching on a per-fiber basis. Because the FXCs can satisfy demand changes by reconfiguring the physical network topology, it can accommodate greater demand variations than traditional fixed networks; this is confirmed by numerical simulations. The reconfigurable network is particularly effective when the network has many nodes with significant demand fluctuations; it accommodates up to 2.5 times more demand than the fixed equivalent.

Recent advances in solid-state technologies have enabled the development of light-emitting diodes (LEDs) with favorable features such as long life expectancy, low-power consumption, and reduced heat dissipation. Visible-light communication (VLC) is a short-range wireless access technology that deploys LEDs as wireless transmitters in addition to their primary task of illumination. The major limitation for the design of high-speed VLC systems is the electrical (modulation) bandwidth of the LED. In this study, we investigate the electrical characteristics of a number of off-the-shelf LEDs. Specifically, we determine their frequency responses and match them to their small-signal models. The electrical bandwidths of measured LEDs vary from 250 kHz to 20 MHz and depend on the emitted color and internal circuitry. As a verification of our measurements, we use the sample LEDs as a transmitter in a VLC system setup and determine the supported data rates. The equivalent circuit model is utilized to compare with the measured modulation characteristic of the LED. Furthermore, the bias current effect on the modulation bandwidth is presented. (C) 2021 Society of Photo-Optical Instrumentation Engineers (SPIE)

Bandwidth demands for datacenter networks continues as performance increases and AI and new HPC workloads explode. Managing power and costs will require a range of solutions from new network architectures to co-packaging.

We propose a traffic r ate m atrix d ecomposition ( TRMD) b ased c onflict free scheduling for a fast optical switching network and show that TRMD outperforms a flow con- trol protocol with <10µs latency and >92% throughput at load of 1.

Based on a DCN with OCS, we propose a pattern-aware scheduling and fast convergence strategy for the distributed machine learning jobs. Experimental results show significant accelerations for completion time and convergence of the jobs.

We propose amplitude caching to optically equalise burst mode traffic without delay stages. Through a fast, optically-switched system prototype, we demonstrate burst- mode penalties can be mitigated to within 0.4 dB at the KR4 HD-FEC level.

We demonstrate SiP switch-enabled server regrouping using bandwidth steering for performance improvement in distributed deep learning training in a Fat-tree testbed. Our proposed SiP switch control scheme enables scaling to large-scale datacenter and HPC systems.

In hybrid electrical/optical networks, packet switching is energy-hungry while circuit switching is inflexible. To better align traffic’s requirements with the hybrid switching capability, we propose QoS-based forwarding schemes, and results show their benefits.

WAN transport is critical to ultra-mobile users need for access to cloud processing and content. Power efficiency continues to improve both due to more efficient hardware and optimized resource utilization through intelligent software and automation. © 2021 The Author(s)

Nanoseconds WDM optical switch is exploited to implement a rack-scale memory disaggregated datacenter network (DCN). Numerical and experimental results validate the disaggregated DCN architecture prototype with 122.3ns network latency, zero packet loss, and error-free operation.

We recently reported hardware-implemented scheduling processors for packet-granular reconfigurable optical circuit-switched networks. Here, we benchmark the performance of the processors under various data center traffic for a range of network loads.

Optical circuit switching is a promising solution for hybrid optical/electrical switching in datacenter networks. We propose two fault-tolerance approaches for the partial circuit-based switching architecture, and results show they can improve the network resilience significantly.

In order to solve the problem that the safety control effect of the traditional electrical equipment circuit system is relatively poor, combined with the big data analysis method, the automatic switch-off technology of the circuit switch of the electrical equipment is studied. According to the power control principle of the peaking unit, a PID algorithm is used to optimize the circuit safety control parameter algorithm. The active power generated by the pulse signal input into the coil drives the automatic control of the circuit switch in the electrical equipment, and accurately detects and controls the operation of the electrical equipment power system, thereby avoiding problems such as circuit failure. Finally, through experimental analysis, it is verified that the effect of the automatic switch-off of the circuit switch of the electrical equipment on the control of the circuit system has been significantly improved based on the analysis of big data, which is an important reference for the development of the electrical industry.

We verify the feasibility of the optical circuit switch architecture for intra-datacentre networks based on spatial super-channels using DP-QPSK, DP-8QAM, and DP-16QAM signals. Simulations clarify the maximum throughput attainable with each modulation format. Experiments demonstrate a switch throughput of 4.3 Pbps.

We demonstrate a $1,024\times 1,024$ wavelength-routing optical switch with switching time under $18\mu \mathrm{s}$ for 256-Gb/s DP-QPSK signals. Wavelength selection at the receivers is achieved by fast widely-tunable (22nm) local oscillators formed using a wavelength bank and newly fabricated silicon ring filters having 5.3-dB fibre-to-fibre insertion loss.

Circuit switched networks with high-bandwidth links are essential to handling ever increasing traffic demands in today's data centers. As these networks incur a non-trivial reconfiguration delay, they are mainly suited for bursty traffic or large flows. To address the reconfiguration delay vs. high-bandwidth tradeoff in circuit networks, an essential traffic scheduling problem is to determine a sequence of network configurations to optimally serve a given traffic. Recent works have addressed this scheduling problem for one-hop traffic in fully-connected circuit networks. In this work, we consider the traffic scheduling problem in general circuit networks with multi-hop traffic load. Such a general model is essential for networks with indirect routes between some nodes, e.g., for recently proposed wireless optical (FSO-based) networks, or to allow multi-hop routes for load balancing. In this context, we develop an efficient algorithm that empirically delivers high network throughput, while also guaranteeing a constant-factor approximation with respect to an objective closely related to network throughput. We generalize our technique and approximation result to more general settings, including to the joint optimization problem of determining flow routes as well as a sequence of network configurations. We demonstrate the effectiveness of our techniques via extensive simulations on synthetic traffic loads based on published traffic characteristics as well as publicly available real traffic loads; we observe significant performance gains in terms of network throughput when compared to approaches based on prior work, and very similar performance to an appropriate upper bound.

We evaluate the feasibility of an optical circuit switch that suits SDM-based intra-datacenter networks. Simulations with 100-Gbps DP-QPSK signals and 200-Gbps DP-16QAM signals clarify the maximum switch throughput attainable with feasible hardware requirements.