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The latest High Efficiency Video Coding standard achieves twice the coding efficiency of the H264 standard through a complex rate-distortion optimization (RDO). The coded bit-streams are produced with context adaptive binary arithmetic coding (CABAC). CABAC itself is a very time-consuming process that includes binarization, context modeling, interval subdivision, renormalization, outstanding bit handling, and context updating. The aim of this research is to speed up the CABAC process through several simplifications. First, we approximate three parts of the CABAC, i.e., interval subdivision, renormalization, and outstanding bit handling, with a piecewise-linear function that is very friendly to hardware implementation. In order to achieve better hardware parallelism, we also improve the coding process at the sub-block level. The context of syntax elements in a sub-block is redistributed to skip the complex calculation of context indexing. We perform context updating at the granularity of sub-blocks so that the data dependency of the context updating is removed completely, and the original serial encoding process is changed to a parallel encoding process. At the same time, we make another simplification for the context modeling of cu_skip_flag. Based on these simplifications, we build a parallel hardware architecture for the rate estimation of the RDO process. This architecture completes the bit estimation of a 32×32 coding tree unit (CTU) in 220.8 nano-seconds, whereas the Bjxntegaard Delta rate increases by only 2.225%. We believe that the proposed architecture can meet the requirements of 8K@120 fps ultra-high-definition videos. This is the first study to simplify the hardware design of rate estimation by changing the context allocation and updating rules.

In a recent paper, Yu et al. obtained convergence and stability results of the K* iterative method for quasistrictly contractive mappings [An iteration process for a general class of contractive-like operators: Convergence, stability and polynomiography. AIMS Mathematics 2021; 6 (7): 6699-6714.]. To guarantee these convergence and stability results, the authors imposed some strong conditions on parametric control sequences which are used in the K* iterative method. The aim of the presented work is twofold: (a) to recapture the aforementioned results without any restrictions imposed on the mentioned parametric control sequences (b) to complete the work of Yu et al. by adding a result regarding the data dependency of the fixed points of quasi-strictly contractive mappings. We also furnish some illustrative examples to support our results. Our work can be considered an important refinement and complement of the work of Yu et al.

Memory caches are being used aggressively in today's data analytics systems such as Spark, Tez, and Piccolo. The significant performance impact of caches and their limited sizes call for efficient cache management in data analytics clusters. However, prevalent data analytics systems employ rather simple cache management policies-notably Least Recently Used (LRU) and Least Frequently Used (LFU)-that are oblivious to the application semantics of data dependency, expressed as directed acyclic graphs (DAGs). Without this knowledge, cache management can, at best, be performed by "guessing" the future data access patterns based on history, which frequently results in inefficient, erroneous caching with a low hit rate and a long response time. Worse still, the lack of data dependency knowledge makes it impossible to retain the all-or-nothing cache property of cluster applications, in that a compute task cannot be sped up unless all the dependent data has been kept in the main memory. In this paper, we propose a novel cache replacement policy, named Least Reference Count (LRC), which exploits the application's data dependency information to optimize the cache management. LRC keeps track of the reference count of each data block, defined as the number of dependent child blocks that have not been computed yet, and always evicts the block with the smallest reference count. Furthermore, we incorporate the all-or-nothing requirement into LRC by coordinately managing the reference counts of all the input data blocks for the same computation. We demonstrate the efficacy of LRC through both empirical analysis and cluster deployments against popular benchmarking workloads. Our Spark implementation shows that, the proposed policies well address the all-or-nothing requirement and significantly improve the cache performance. Compared with LRU and a recently proposed caching policy called MEMTUNE, LRC improves the caching performance of typical workloads in production clusters by 22% and 284%, respectively.

Recently, edge-cloud has attracted much attention by its promising prospect in terms of facilitating the benefits of edge and cloud together. It is promising for urban video systems that require efficient and effective processing for their intelligent monitoring drives on various ends, like sky drones and land cameras. For instance, to support crowd recognition for public safety, the tasks to crowd recognition need to be placed into all processing nodes in the video systems for processing effectively. This is a challenging problem to facilitate the edge-cloud orchestrated scenarios. However, the variability of tasks based on their complexities is not considered fully in existing strategies. In this regard, we model and analyse task placement for crowd recognition in edge-cloud intelligent video systems. Then, our strategies are proposed which are referred to Node-Graph based Task Placement (NGTP) and Cluster-Graph based Task Placement (CGTP). Specifically, with the help of data dependencies, NGTP utilises the greedy approach with node graphs in the centralised way for general scenarios. Comparatively, CGTP utilises data dependency and similarity for task placing in the decentralised way for emergency scenarios. The experiments demonstrate the superior and effectiveness performance in forming tasks cost and running time of our proposed approaches.

Scientific workflows have been an increasingly important research area of distributed systems (such as cloud computing). Researchers have shown an increased interest in the automated processing scientific applications such as workflows. Recently, Function as a Service (FaaS) has emerged as a novel distributed systems platform for processing non-interactive applications. FaaS has limitations in resource use (e.g., CPU and RAM) as well as state management. In spite of these, initial studies have already demonstrated using FaaS for processing scientific workflows. DEWE v3 executes workflows in this fashion, but it often suffers from duplicate data transfers while using FaaS. This behaviour is due to the handling of intermediate data dependencies after and before each function invocation. These data dependencies could fill the temporary storage of the function environment. Our approach alters the job dispatch algorithm of DEWE v3 to reduce data dependency transfers. The proposed algorithm schedules jobs with precedence requirements to primarily run in the same function invocation. We evaluate our proposed algorithm and the original algorithm with small- and large-scale Montage workflows. Our results show that the improved system can reduce the total workflow execution time of scientific workflows over DEWE v3 by about 10\% when using AWS Lambda.

In recent years, intelligent condition-based monitoring of rotary machinery systems has become a major research focus of machine fault diagnosis. In condition-based monitoring, it is challenging to form a large-scale well-annotated dataset due to the expense of data acquisition and costly annotation. The generated data have a large number of redundant features which degraded the performance of the machine learning models. To overcome this, we have utilized the advantages of minimum redundancy maximum relevance ( mRMR ) and transfer learning with a deep learning model. In this work, mRMR is combined with deep learning and deep transfer learning framework to improve the fault diagnostics performance in terms of accuracy and computational complexity. The mRMR reduces the redundant information from data and increases the deep learning performance, whereas transfer learning, reduces a large amount of data dependency for training the model. In the proposed work, two frameworks, i.e., mRMR with deep learning and mRMR with deep transfer learning, have explored and validated on CWRU and IMS rolling element bearings datasets. The analysis shows that the proposed frameworks can obtain better diagnostic accuracy compared to existing methods and can handle the data with a large number of features more quickly.

Static malware detection approaches are time-consuming and cannot deal with code obfuscation techniques. Dynamic malware detection approaches, on the other hand, address these two challenges, however, suffer from behavioral ambiguity, such as the system calls obfuscation. In this paper, we introduce Markhor, a dynamic and behavior-based malware detection approach. Markhor uses system call data dependency and system call control dependency sequences to create a weighted list of malicious patterns. The list is then used to determine the malicious processes. Next, the similarity of a file system call sequences to a malicious pattern is extracted based on a fuzzy algorithm and the file nature is determined. The evaluation results reveal the efficiency of Markhor in terms of accuracy (0.982), precision (0.976), and F-measure (0.982).

Scientific computations with a wide range of applications in domains such as developing vaccines, forecasting the weather, predicting natural disasters, simulating aerodynamics of spacecraft, and exploring oil resources, create the main workloads of supercomputers. The key integration of such scientific computations is modeling physical phenomena that are done with the aid of partial differential equations (PDEs). Solving PDEs on supercomputers, even with those equipped with GPUs, consumes a large amount of power and yet is not as fast as desired. The main reason behind such slow processing is data dependency. The key challenge is that software techniques cannot resolve these dependencies, therefore, such applications cannot benefit from the parallelism provided by processors such as GPUs. Our key insight to address this challenge is that although we cannot resolve the dependencies, we can reduce their negative impacts by using hardware/software co-optimization. To this end, we propose breaking down the data-dependent operations into two groups of operations: a majority of parallelizable and the minority of data-dependent operations. We execute these two groups in the desired order: first, we put together all parallelizable operations and execute them all, subsequently; then, we switch to execute the small data-dependent part. As long as the data-dependent part is small, we can accelerate them by using fast hardware mechanisms. Besides, our proposed hardware mechanisms guarantee quickly switching between the two groups of operations. To follow the same order of execution, dictated by our software mechanism, and implemented in hardware, we also propose a new low-overhead compression format – sparsity is another attribute of PDEs that require compression. Furthermore, the core generic architecture of our proposed hardware allows the execution of other applications including sparse matrix-vector multiplication (SpMV) and graph algorithms. The key feature of the proposed hardware is partial reconfigurability, which on one hand, facilitates the execution of data-dependent computations, and on the other hand, allows executing broad application without changing the entire configuration. Our evaluations show that compared to GPUs, we achieve an average speedup of 15.6× for scientific computations while consuming 14× less energy.

Null pointer dereference (NPD) is a widespread vulnerability that occurs whenever an executing program attempts to dereference a null pointer. NPD vulnerability can be exploited by hackers to maliciously crash a process to cause a denial of service or execute an arbitrary code under specific conditions. This typical taint-style vulnerability requires an accurate data dependency analysis to trace whether a source is propagated to a sensitive sink without proper sanitization. The primary challenge in data dependency analysis is pointer aliasing, which may significantly affect the vulnerability detection accuracy. Although there have been many studies and open-source tools, they still have limitations when detecting a real-world binary. In this paper, we propose a static binary analysis approach to detect an NPD vulnerability. To improve detection accuracy and practicality, we first identify two challenges that affect the accuracy of binary NPD detection: (i) pointer aliasing, and (ii) untrusted source identification. Then we implement a prototype of the proposed approach, NPDHunter, and evaluate it against 318 test cases provided by Juliet Test Suite v1.3. For the Juliet dataset, NPDHunter is accurate in detecting NPDs and generates 0% false negatives; as compared to bap-toolkit and cwe_checker, which have false-negative rates of 70.89% and 89.81%, respectively. We also evaluate NPDHunter for real-world binaries which recently reported NPD vulnerability. We have analyzed XNU kernel (large-scale), Redis, Bitlbee, libredwg, and libvncserver binaries and NPDHunter can detect all NPD cases, which justifies its usefulness for real-world binaries; compiled for x86_64 architecture.

The aim of this paper is to define a new iteration scheme $N^v_1$ which converges to a fixed point faster than some previously existing methods such as Picard, Mann, Ishikawa, Noor, SP, CR, S, Picard-S, Garodia, $K$ and $K^*$ methods etc. The effectiveness and efficiency of our algorithm is confirmed by numerical example and some strong convergence, weak convergence, $T$-stability and data dependence results for contraction mapping are also proven. Moreover, it is shown that differential equation with retarted argument is solved using $N^v_1$ iteration process.

To overcome the limitation of standalone edge cloud in terms of computing power and resource, a concept of distributed edge cloud has been introduced, where application tasks are distributed to multiple edge clouds for collaborative processing. To maximize the effectiveness of the distributed edge cloud, we formulate an optimization problem of task allocation to minimize the application completion time. To mitigate high complexity overhead in the formulated problem, we devise a low-complexity heuristic algorithm called dependency-aware task allocation (DATA) algorithm. Evaluation results demonstrate that DATA can reduce the application completion time up to by 15%–32% compared to conventional dependency-unaware task allocation schemes.

The state-of-the-art convolutional neural network (CNN) structures present growing irregularity in the sense of layer connections, which derives from the innovative manual designs and the recently proposed neural architecture searching approaches. Such irregular structures improve recognition accuracy, but also bring challenges for hardware deployment, especially on CNN accelerators with regular architectures: 1) the complicated data dependency makes it nontrivial to decide the data reuse strategy between layers and 2) since the execution order of each network is not unique, the choice of layer scheduling, memory allocating, and loop tiling strategies greatly impact the hardware performance. These challenges cannot be solved by the existing CNN schedulers, which mainly focuses on the dataflow of a single layer. In this work, we propose a comprehensive framework to analyze and solve the mapping of an arbitrarily connected CNN network to specific hardware accelerators. We propose: 1) a dynamic programming and node-clustering-based DAG partitioning approach to efficiently exploit interlayer data reuse and 2) a subgraph scheduling and on-chip memory allocating strategy to find the optimal execution order. With the modeling of CNN accelerators, we also propose a loop tiling approach for fused layers. An automated framework is established to generate binary machine codes from original CNN models produced by mainstream deep learning frameworks, which can process large-scale CNNs with more than 1000 layers in only a few minutes. Experiments based on state-of-the-art accelerators (e.g., NVDLA) show that our techniques greatly reduce the external data transfer of interlayer dependencies and bring significant performance improvement over existing approaches.

Machine learning over graphs has been emerging as powerful learning tools for graph data. However, it is challenging for industrial communities to leverage the techniques, such as graph neural networks (GNNs), and solve real-world problems at scale because of inherent data dependency in the graphs. As such, we cannot simply train a GNN with classic learning systems, for instance, parameter server that assumes data parallelism. Existing systems store the graph data in-memory for fast accesses either in a single machine or graph stores from remote. The major drawbacks are three-fold. First, they cannot scale because of the limitations on the volume of the memories, or the bandwidth between graph stores and workers. Second, they require extra development of graph stores without well exploiting mature infrastructures such as MapReduce that guarantee good system properties. Third, they focus on training but ignore optimizing the performance of inference over graphs, thus makes them an unintegrated system. In this paper, we design AGL, a scalable and integrated system, with fully-functional training and inference for GNNs. Our system design follows the message passing scheme underlying the computations of GNNs. We design to generate the K -hop neighborhood, an information-complete subgraph for each node, as well as do the inference simply by merging values from in-edge neighbors and propagating values to out-edge neighbors via MapReduce. In addition, the K -hop neighborhood contains information-complete subgraphs for each node, thus we simply do the training on parameter servers due to data independence. Our system AGL, implemented on mature infrastructures, can finish the training of a 2-layer GNN on a graph with billions of nodes and hundred billions of edges in 14 hours, and complete the inference in 1.2 hours.

Matrix Factorization (MF) based on Stochastic Gradient Descent (SGD) is a powerful machine learning technique to derive hidden features of objects from observations. In this article, we design a highly parallel architecture based on Field-Programmable Gate Array (FPGA) to accelerate the training process of the SGD-based MF algorithm. We identify the challenges for the acceleration and propose novel algorithmic optimizations to overcome them. By transforming the SGD-based MF algorithm into a bipartite graph processing problem, we propose a 3-level hierarchical partitioning scheme that enables conflict-minimizing scheduling and processing of edges to achieve significant speedup. First, we develop a fast heuristic graph partitioning approach to partition the bipartite graph into induced subgraphs; this enables to efficiently use the on-chip memory resources of FPGA for data reuse and completely hide the data communication between FPGA and external memory. Second, we partition all the edges of each subgraph into non-overlapping matchings to extract the maximum parallelism. Third, we propose a batching algorithm to schedule the execution of the edges inside each matching to reduce the memory access conflicts to the on-chip RAMs of FPGA. Compared with non-optimized FPGA-based baseline designs, the proposed optimizations result in up to 60× data dependency reduction, 4.2× bank conflict reduction, and 15.4× speedup. We evaluate the performance of our design using a state-of-the-art FPGA device. Experimental results show that our FPGA accelerator sustains a high computing throughput of up to 217 billion floating-point operations per second (GFLOPS) for training very large real-life sparse matrices. Compared with highly-optimized GPU-based accelerators, our FPGA accelerator achieves up to 12.7× speedup. Based on our optimization methodology, we also implement a software-based design on a multi-core platform, which demonstrates 1.3× speedup compared with the state-of-the-art multi-core implementation.

Multilevel latent class analysis (MLCA) has been increasingly used to investigate unobserved population heterogeneity while taking into account data dependency. Nonparametric MLCA has gained much p...

A Weighted Essentially Non-Oscillatory scheme (WENO) is a solution to hyperbolic conservation laws, suitable for solving high-density fluid interface instability with strong intermittency. These problems have a large and complex flow structure. To fully utilize the computing power of High Performance Computing (HPC) systems, it is necessary to develop specific methodologies to optimize the performance of applications based on the particular system's architecture. The Sunway TaihuLight supercomputer is currently ranked as the fastest supercomputer in the world. This article presents a heterogeneous parallel algorithm design and performance optimization of a high-order WENO on Sunway TaihuLight. We analyzed characteristics of kernel functions, and proposed an appropriate heterogeneous parallel model. We also figured out the best division strategy for computing tasks, and implemented the parallel algorithm on Sunway TaihuLight. By using access optimization, data dependency elimination, and vectorization optimization, our parallel algorithm can achieve up to 172X speedup on one single node, and additional 58X speedup on 64 nodes, with nearly linear scalability.

In this paper, we extend the study of an iteration process introduced by Thakur-Thakur-Postolache [J. Inequal. Appl., (2014), 147–155] from the class of nonexpansive operators to the more general c...

In business process collaboration (BPC), especially when it comes to message communication and data exchange, there are complex data dependencies among sender process, receiver process and messages. However, each participant of the overall BPC develops its part independently as a service, including its own communication part and data flow. As a result, data flow errors across processes may occur easily. In this article, we propose a method based on BPMN to detect these errors caused by data dependency violations. Our method is inspired by the study of detecting data flow errors within a single process and focuses on a subset of the elements of the BPC model, without having to consider the complete set. In particular, we define a set of data flow error patterns by analyzing and formalizing data dependencies in order to clearly clarify and identify errors. Then we give the corresponding automatic detection algorithm. Finally, through two evaluations, we demonstrate the effectiveness of our proposal.

Simulated quantum annealing (SQA) is a probabilistic approximation method to find a solution for a combinatorial optimization problem using digital computers. The processing time of SQA increases exponentially with the number of variables. Therefore, acceleration of SQA is regarded as a very important topic. However, parallel implementation is difficult due to the serial nature of the quantum Monte Carlo algorithm used in SQA. In this paper, we propose a method to implement SQA in parallel on a GPU while preserving the data dependency. According to the experimental results, we have achieved over 97 times speed-up while maintaining the same accuracy-level compared to a single-core CPU implementation.

For the fault diagnosis problems of rotating machinery in the real industrial practice, measurement data with imbalanced class distributions negatively affect the diagnostic performance of most conventional machine learning classification algorithms since equal cost weights are assigned to different fault classes. Meanwhile, the widely used traditional data generation methods for the imbalanced data problem are limited by data dependencies over time continuity. To fill this research gap, this paper develops a new diagnostic framework based on the adversarial neural networks (GAN) and multi-sensor data fusion technique to generate new synthetic data for data compensation purpose. Two different practice modes are designed based on this framework according to the position logic of the data fusion, namely a Pre-fusion GAN mode and a Post-fusion GAN mode. More concretely, without data pre-processing, the designed generator generates synthetic data to puzzle the discriminator and the synthetic data that out-trick the discriminator can be used to compensate the minor class. To avoid data dependency and to ensure the generality of the proposed framework, the network modelling are trained with a more practical approach where the training and test data are obtained under different rotating speeds. Two imbalanced data sets on the rotating machinery, one benchmark public rolling bearing data set and another gear box data set acquired in our lab, are used to validate the proposed method. The performance is examined through a wide range of data imbalanced ratios (as high as 30:1), and compared with other state-of-the-art methods. The experiment results conclude that the proposed Pre-fusion GAN and Post-fusion GAN frameworks both have good performance on the imbalanced fault diagnosis of rotating machinery.

Density accumulation is a widely-used primitive operation in physical design, especially for placement. Iterative invocation in the optimization flow makes it one of the runtime bottlenecks. Accelerating density accumulation is challenging due to data dependency and workload imbalance. In this paper, we propose efficient CPU/GPU kernels for density accumulation by decomposing the problem into two phases: constant-time density collection for each instance and a linear-time prefix sum. We develop CPU and GPU dedicated implementations, and demonstrate promising efficiency benefits on tasks from large-scale placement problems.

The degradation of stability index within smart grid leads to incorrect power generation and poor load balancing. The remote data dependency of the central energy management system (CEMS) causes communication delay that further leads to poor synchronization within the system. This becomes worse in the presence of cyber-attacks such as stealth or false data injection attack (FDIA). We used dynamic estimation to obtain state data after the inception of false data attack and analyzed its impact on the stability index of the smart grid. A lookup table was constructed based on the fluctuations within the voltage estimates of IEEE-Bus system. An index number was assigned to output estimates at the bus that highlights the level of severity within the grid. We used IEEE-57 Bus using MATLAB to capture and plot the results related to voltage estimates, latency, and inception time delay. The results demonstrate a clear relationship between stability index and state estimates especially when the system is under the influence of a cyber-attack.

The currently widely used backpropagation (BP) training algorithm requires that all trainable weights in a deep neural network (DNN) be stored in memory and used sequentially in the backward path, which makes training parallelization extremely challenging and also incurs significant memory and computing overheads. Although emerging ReRAM-based computing has demonstrated great potential for DNN acceleration, state-of-the-art designs suffer from >60% energy overhead for analog-to-digital converters (ADCs). In this work, we propose PUFFIN, an efficient DNN training accelerator for Direct Feedback Alignment (DFA). PUFFIN leverages DFA to overcome the limitation of long-range data dependency required by BP and executes an L -layer DNN training in parallel in an (L+2)-stage pipeline. We implement PUFFIN using Ferroelectric Field-Effect Transistors (FeFET) due to their high performance and low-power operation. To further improve the power efficiency, we propose a random number generator (RNG) based on the statistical switching in FeFET device and an ultra-low power FeFET-based ADC. Compared to previous ReRAM-based training accelerators, PUFFIN achieves 1.3 × speedup and 2.5× improvement on power efficiency.

Wearable sensors have been explored as an alternative for real-time monitoring of cattle feeding behavior in grazing systems. To evaluate the performance of predictive models such as machine learning (ML) techniques, data cross-validation (CV) approaches are often employed. However, due to data dependencies and confounding effects, poorly performed validation strategies may significantly inflate the prediction quality. In this context, our objective was to evaluate the effect of different CV strategies on the prediction of grazing activities in cattle using wearable sensor (accelerometer) data and ML algorithms. Six Nellore bulls (average live weight of 345 ± 21 kg) had their behavior visually classified as grazing or not-grazing for a period of 15 d. Elastic Net Generalized Linear Model (GLM), Random Forest (RF), and Artificial Neural Network (ANN) were employed to predict grazing activity (grazing or not-grazing) using 3-axis accelerometer data. For each analytical method, three CV strategies were evaluated: holdout, leave-one-animal-out (LOAO), and leave-one-day-out (LODO). Algorithms were trained using similar dataset sizes (holdout: n = 57,862; LOAO: n = 56,786; LODO: n = 56,672). Overall, GLM delivered the worst prediction accuracy (53%) compared with the ML techniques (65% for both RF and ANN), and ANN performed slightly better than RF for LOAO (73%) and LODO (64%) across CV strategies. The holdout yielded the highest nominal accuracy values for all three ML approaches (GLM: 59%, RF: 76%, and ANN: 74%), followed by LODO (GLM: 49%, RF: 61%, and ANN: 63%) and LOAO (GLM: 52%, RF: 57%, and ANN: 57%). With a larger dataset (i.e., more animals and grazing management scenarios), it is expected that accuracy could be increased. Most importantly, the greater prediction accuracy observed for holdout CV may simply indicate a lack of data independence and the presence of carry-over effects from animals and grazing management. Our results suggest that generalizing predictive models to unknown (not used for training) animals or grazing management may incur poor prediction quality. The results highlight the need for using management knowledge to define the validation strategy that is closer to the real-life situation, i.e., the intended application of the predictive model.

Floods are the most frequent disasters, causing widespread damage resulting in loss of lives and properties. In this paper, we present Sinotech Engineering Consultants Hydrodynamic (SEC-HY21) simulation modeling to predicted floods and estimate their damage efficiently. However, SEC-HY21 still suffers from the slow simulation rate due to its data dependency structure which does not make the numerical model of SEC-HY21 parallelizable. In this research, a near real-time flood simulation has been reached by Compute Unified Device Architecture (CUDA) parallel implementation on NVIDIA Graphics Processing Unit (GPU) to accelerate the performance of the slowest module in the SEC-HY21 package, namely iFlux. The experimental results have shown that the CUDA-based parallel implementation has made the SEC-HY21 simulation modeling ∼ 14× faster than before.

Admission chance prediction helps in many ways for candidates such as estimation of results, saving time and effort for higher acceptance chance, selecting the right school and making a good training plan. Admission chance prediction is also very valuable to prepare a good training plan since the physical ability test is one of the most important criteria for admission. Among many Machine Learning approaches, we only used Support Vector Machine (SVM), Single Decision Tree (SDT). In this study, these approaches were applied to train models on the dataset of 403 candidates who applied in 2018. These models were compared to each other for better accuracy and will be used them in the following years. The results were analyzed with K-fold cross-validation to decrease data dependency and increase reliability.

The co-existence of activation sparsity and model sparsity in convolutional neural network (CNN) models makes sparsity-aware CNN hardware designs very attractive. The existing sparse CNN accelerators utilize intersection operation to search and identify the key positions of the matched entries between two sparse vectors, and hence avoid unnecessary computations. However, these state-of-the-art designs still suffer from three major architecture-level drawbacks, including 1) hardware cost for the intersection operation is high; 2) frequent stalls of computation phase due to strong data dependency between intersection and computation phases; and 3) unnecessary data transfer incurred by the explicit intersection operation. By leveraging the knowledge of the complete sparse 2-D convolution, this paper proposes two key ideas that overcome all of the three drawbacks. First, an implicit on-the-fly intersection is proposed to realize the optimal solution for intersection between one static stream and one dynamic stream, which is the case for sparse neural network inference. Second, by leveraging the global computation structure of 2--D convolution, we propose a specialized computation reordering to ensure that the activation is only transferred if necessary and only once. Based on these two key ideas, we develop GoSPA, an energy-efficient high-performance Globally Optimized SParse CNN Accelerator. GoSPA is implemented with CMOS 28nm technology. Compared with the state-of-the-art sparse CNN architecture, GoSPA achieves average 1.38X, 1.28X, 1.23X, 1.17X, 1.21X and 1.28X speedup on AlexNet, VGG, GoogLeNet, MobileNet, ResNet and ResNeXt workloads, respectively. Also, GoSPA achieves 5.38X, 4.96X, 4.79X, 5.02X, 4.86X and 2.06X energy efficiency improvement on AlexNet, VGG, GoogLeNet, MobileNet, ResNet and ResNeXt, respectively. In more comprehensive comparison including DRAM access, GoSPA also shows significant performance improvement over the existing designs.

As modern GPU workloads grow in size and complexity, there is an ever-increasing demand for GPU computational power. Emerging workloads contain hundreds or thousands of GPU kernel launches, which incur high overheads, and exhibit data-dependent behavior between kernels, which requires synchronization, leading to GPU under-utilization. Task-based execution models have been proposed to solve these issues, but they require significant programmer effort to port applications to proprietary task-based programming models in order to specify tasks and task dependencies. To address this need, we propose BlockMaestro, a software-hardware solution that combines command queue reordering, kernel-launch-time static analysis, and runtime hardware support to dynamically identify and resolve thread-block level data dependencies between kernels. Through static analysis of memory access patterns at kernel-launch-time, BlockMaestro can extract inter-kernel thread block-level data dependencies. BlockMaestro also introduces kernel pre-launching to reduce the kernel launch overheads experienced by multiple dependent kernels. Correctness is enforced by dynamically resolving thread block-level data dependency at runtime through hardware support. BlockMaestro achieves an average speedup of 51.76% (up to 2.92x) on data-dependent benchmarks, and requires minimal hardware overhead.

Newly introduced Iris recognition systems (IRSs) run on serial processors. In this paper, an alternative method has been introduced for parallel processing on Graphic processing unit (GPU) with Compute unified device architecture (CUDA) in order to increase the speed of the system. The IRS has two main parallel processing criteria, which include the division of computations into hundreds of independent units and the time of calculation more than the time of transferring from the GPU. The IRS is divided into six stages including imaging, pre-processing, segmentation, normalization, feature extraction, and matching. In order to increase speed and accuracy, two stages of iris segmentation and matching play an important role in the IRS. In this paper parallel execution of an identical algorithm for these two stages has been used. The reason for paralleling the iris segmentation stage and their low speed matching is due to a great amount of information in the iris database, plenty of calculations and lack of data dependency in these two stages. For parallelism at the segmentation stage, for each radius, the Hough transform (HT) is a processor, and in the matching stage two parts are considered: The first part consists of 32 actions comparing the input code with the database code in parallel and in the second part 2048 bits with the use of threads on each processor is performed in two sub-sections in pairs of bits and in parallel with each other. Finally, the two-way coding is achieved. In compare of existing methods, this method has rather more accurate and is also superior in terms of processing time on the GPU with CUDA. The results of the implementation of the above method on the images in UBIRIS, BATH, CASIA and MMUI databases show that the proposed method has a precision accuracy of 99.12%, 97.98%, 98.80% and 98.34%, respectively, and the average speedup for parallel processing of images in the database in the proposed method on the GPU with CUDA are 18.8, 14.7, 18, and 19 times, respectively.

This paper presents a new method for parallelizing geodesic algorithms on triangle meshes. Using the half-edge data structure, we define the propagation dependency graph to characterize data dependency in computing geodesics. Then, we design an active strategy such that the vertices and half-edges on the wavefront take the initiative to collect their input data and then propagate windows and update geodesic information in their own memory space. As a result, all the read and write operations can be carried out simultaneously. Our method, named AWP, works for both exact (e.g., the CH algorithm) and approximate (e.g., the fast marching method) geodesic algorithms. Our implementation on various NVIDIA GPUs exhibit perfect linear speedup, i.e., doubling the computational power (i.e., FLOPS) doubles the speed. We prove that the AWP-CH algorithm runs in O(n2∕min(C,n)) time, where n and C are the numbers of faces and cores, respectively. Evaluation on GTX Titan XP shows that AWP-CH empirically runs in np time, p∈[1.25,1.35], for real-world models with n≤107 and anisotropy measure τ≤2.0. Thanks to its perfect efficiency and the trend of increasing the number of processors in graphics hardware, we believe that the actual performance of AWP can be further improved in the near future. Ministry of Education (MOE) This project is partially supported by the National Natural Science Foundation of China (Grant No. 61402322), Tianjin Research Program of Application Foundation and Advanced Technology, China (Grant No, 15JCQNJC00300) and Singapore Ministry of Education Grant RG26/17.

The rapid development of modern information technology has resulted in a sharp increase in the rate of data growth. This results in a lack of storage space and network bandwidth. Compression technology is typically implemented to mitigate the increasing demand for storage and the transmission cost of data. However, data compression may impose a significant computational burden on the CPU, which results in a degradation of system performance. To solve this problem, a hardware offloading technique can be used. Hardware offloading not only reduces the computational load imposed on the CPU but also improves the performance of the compression algorithm by exploiting hardware parallelism. However, data-hazards associated with the compression algorithm hinders achieving the achievement of a high degree of parallelism. DEFLATE is a widely used lossless compression scheme. Many studies have attempted to eliminate the data dependencies associated with compression algorithms. Unfortunately, existing studies do not address data dependency elimination in Huffman encoding. Our work aims to parallelize Huffman encoding by solving the data-hazard problem in the algorithm. To address the data dependency that exists in the Huffman encoding algorithm, a new data representation for the intermediate data generated during data compression is proposed. The effectiveness of the proposed scheme was evaluated via the implementation of an architecture which applied the approach in the field-programmable gate array (FPGA) platform. Experimental results show that the proposed scheme can increase the throughput of the compressor by up to 14.4%.

Recently, the authors have proposed a scalable holistic scheduling approach for time-triggered applications on FlexRay, under end-to-end deadline and data dependency constraints. This approach divides the problem to two sub-problems that can be solved separately. The first sub-problem optimally schedules the set of messages to minimize number of used slots, and with respect to information exchanges between tasks and messages, end-to-end deadlines and FlexRay protocol constraints. The second sub-problem optimally schedules the set of tasks to minimize tasks response times, with respect to the solution returned by the first sub-problem. In this paper, our goal is to increase the scalability of our solution to each sub-problem. We propose a greedy heuristic approach for the first sub-problem that can find feasible solutions at a low runtime cost. In addition, to resolve assignment conflicts, we apply rescheduling the conflicted application with offset modification and priority promotion procedures. Furthermore, we show that the task scheduling in the second sub-problem can be divided into K independent child sub-problems, where K is the number of ECUs. Our experiments show high scalability and efficiency of our approaches comparing with our optimization-based approaches in the previous work.

In this paper, we introduce a new discontinuous operator and investigate the existence and uniqueness of fixed points for the operators in complete metric spaces. We also provide rate of co...

Well plugging and abandonment are necessitated to ensure safe closure of a non-producing offshore asset. Little or no condition monitoring is done after the abandonment operation, and data are often unavailable to analyze the risks of potential leakage. It is therefore essential to capture all inherent and evolving hazards associated with this activity before its implementation. The current probabilistic risk analysis approaches such as fault tree, event tree and bowtie though able to model potential leak scenarios; these approaches have limited capabilities to handle evolving well conditions and data unavailability. Many of the barriers of an abandoned well deteriorates over time and are dependent on external conditions, making it necessary to consider advanced approaches to model potential leakage risk. This paper presents a Bayesian network-based model for well plugging and abandonment. The proposed model able to handle evolving conditions of the barriers, their failure dependence and, also uncertainty in the data. The model uses advanced logic conditions such as Noisy-OR and leaky Noisy-OR to define the condition and data dependency. The proposed model is explained and tested on a case study from the Elgin platform's well plugging and abandonment failure.

Rate-compatible modulation (RCM) achieves seamless rate adaptation under time-varying channels by varying the number of transmitted symbols at a small granularity. The implementation of effective decoders based on the belief propagation (BP) algorithm suffers from the varying number of symbols and highly complex symbol nodes. Considering these RCM-specific characteristics, we present a top–down design methodology, including decoding algorithm, mapping matrix construction, and hardware implementation. The layered BP algorithm provides the potential to implement the decoders that fine-tune the decoding throughput according to the number of symbols. To mitigate the impact of inter-layer data dependency on decoding throughput and facilitate the implementation of low parallelism decoders, a construction and optimization algorithm is proposed to obtain the two-level quasi-cyclic matrices with small sub-matrix size. The proposed algorithm and matrix are applied to a partially parallel RCM decoder for a ${5544 \times 5544}$ matrix on a field-programmable gate-array (FPGA) device. A memory access structure that requires only one barrel shifter is used to improve area efficiency. The post-route results show that the decoder achieves a throughput of 377 M ~ 1100 Mbit/s at six iterations with a clock frequency of 218 MHz.

In classification theory, it is generally assumed that the data are independent and identically distributed. However, in many practical applications, we face a set of observations that are collected sequentially with a dependence structure among samples. The primary focus of this investigation is to construct the optimal Bayesian classifier (OBC) when the training observations are serially dependent. To model the effect of dependency, we assume the training observations are generated from $\text{VAR }(p)$ , which is a multidimensional vector autoregressive process of order $p$ . At the same time, we assume there exists uncertainty about parameters governing the $\text{VAR}(p)$ model. To model this uncertainty, we assume that model parameters (coefficient matrices) are random variables with a prior distribution, and find the resulting OBC under the assumption of known covariance matrices of white-noise processes. We employ simulations using both synthetic and real data to demonstrate the efficacy of the constructed OBC.

In this article, we introduce a new class of contractive mappings and study analytical and computational aspects of a special case of Jungck-Khan iterative algorithm generated by this class...

We present Lerna, an end-to-end tool that automatically and transparently detects and extracts parallelism from data-dependent sequential loops. Lerna uses speculation combined with a set of techniques including code profiling, dependency analysis, instrumentation, and adaptive execution. Speculation is needed to avoid conservative actions and detect actual conflicts. Lerna targets applications that are hard-to-parallelize due to data dependency. Our experimental study involves the parallelization of 13 applications with data dependencies. Results on a 24-core machine show an average of 2.7× speedup for micro-benchmarks and 2.5× for the macro-benchmarks.

Non-dominated sorting is a crucial component of Pareto-based multi- and many-objective evolutionary algorithms. As the number of objectives increases, the execution time of a multi-objective evolutionary algorithm increases, too. Since multi-objective evolutionary algorithms normally have a low data dependency, research-ers have increasingly adopted parallel programming techniques to reduce their execution time. Evidently, it is also desirable to parallelize non-dominated sorting. There are some recent proposals which focus on the parallelization of non-dominated sorting, with a particular emphasis on a very well-known approach called fast non-dominated sorting. In this paper, however, we explore the scope of parallelism in an approach called divide-and-conquer based non-dominated sorting (DCNS), which we recently introduced. This paper explores the parallelism from a theoretical point of view. The parallelization of the DCNS approach has been explored considering the PRAM-CREW (Parallel Random Access Machine, Concurrent Read Exclusive Write) model. The analysis of parallel algorithms is usually carried out under the assumption that an unbounded number of processors are available. So, in our analysis, we have also considered the same assumption. The time and space complexities of the parallel version of the DCNS approach is obtained in different scenarios. The time complexity of the parallel version of the DCNS approach in different scenarios is proved to be $$\mathcal {O}(\log M + N)$$ . We have also obtained the maximum number of processors which can be required by the parallel version of the DCNS approach. The comparison of the parallel version of the DCNS approach with respect to some other approaches is also performed.

Smith–Waterman algorithm (SW) is a popular dynamic programming algorithm widely used in bioinformatics for local biological sequence alignment. Due to the $$O(n^2)$$ high time and space complexity of SW and growing size of biological data, it is crucial to accelerate SW for high performance. In view of the GPU high efficiency in science computation, many existing studies (e.g., CUDAlign, CUDASW++) speedup SW with GPU. However, the strong data dependency makes SW communication intensive, and the previous works fail to fully leverage the heterogeneous capabilities of the GPU machine for either the neglect of the CPU ability or the low bandwidth of PCI-e. In this paper, we propose ASW, which aims at accelerating SW algorithm with accelerated processing unit (APU), a heterogeneous processor integrates CPU and GPU in a single die and share the same memory. This coupled CPU–GPU architecture is more suitable for frequent data exchanging due to the elimination of PCI-e bus. For the full utilization of both CPU and GPU in APU system, ASW partitions the whole SW matrix into blocks and dynamically dispatches each block to CPU and GPU for the concurrent execution. A DAG-based dynamic scheduling method is presented to dispatch the workload automatically. Moreover, we also design a time cost model to determine the partition granularity in the matrix division phase. We have evaluated ASW on AMD A12 platform and our results show that ASW achieves a good performance of 7.2 GCUPS (gigacells update per second).

Today enterprises have massive stream data that require to be processed in real time due to data explosion in recent years. Spark Streaming as an emerging system is developed to process real time stream data analytics by using micro-batch approach. The unified programming model of Spark Steaming leads to some unique benefits over other traditional streaming systems, such as fast recovery from failures, better load balancing and resource usage. It treats the continuous stream as a series of micro-batches of data and continuously process these micro-batch jobs. However, efficient scheduling of micro-batch jobs to achieve high throughput and low latency is very challenging due to the complex data dependency and dynamism inherent in streaming workloads. In this paper, we propose A-scheduler, an adaptive scheduling approach that dynamically schedules parallel micro-batch jobs in Spark Streaming and automatically adjusts scheduling parameters to improve performance and resource efficiency. Specifically, A-scheduler dynamically schedules multiple jobs concurrently using different policies based on their data dependencies and automatically adjusts the level of job parallelism and resource shares among jobs based on workload properties. Furthermore, we integrate dynamic batching technique with A-Scheduler to further improve the overall performance of the customized Spark Streaming system. It relies on an expert fuzzy control mechanism to dynamically adjust the length of each batch interval in response to time-varying streaming workload and system processing rate. We implemented A-scheduler and evaluated it with a real-time security event processing workload. Our experimental results show that A-scheduler with dynamic batching can reduce end-to-end latency by 38 percent and meanwhile improve workload throughput and energy efficiency by 23 and 15 percent, respectively, compared to the default Spark Streaming scheduler.

Atrial fibrillation (AF) is an arrhythmia that can cause blood clot and may lead to stroke and heart failure. To detect AF, deep learning-based detection algorithms have recently been developed. However, deep learning models were often trained with limited datasets and were evaluated within the same datasets, which makes their performance generally drops on the external datasets, known as data dependency. For this study, three different databases from PhysioNet were used to investigate the data dependency of deep learning-based AF detection algorithm using the residual neural network (Resnet). Resnet 18, 34, 50 and 152 model were trained with raw electrocardiogram (ECG) signal extracted from independent database. The highest accuracy was about 98–99% which is evaluation results of test dataset from the own database. On the other hand, the lowest accuracy was about 53–92% which was evaluation results of the external dataset extracted from different source. There are data dependency according to the train dataset and the test dataset. However, the data dependency decreased as a large amount of train data.

This paper presents a reconfigurable LDPC decoder implementation fully compliant with all the configurations in the 5G NR standard. Based on the row-based layered normalized Min-Sum (NMS) algorithm, the optimization approaches are proposed to solve the data dependency hazard in the pipeline process. The proposed instruction-level reordering diminishes the redundant latency of our pipelined decoder architecture. Moreover, the proposed data-level rescheduling optimizes the decoding sequence to remove the remaining pipeline stalls in the high- throughput design without decoding performance degradation. Evaluated in Xilinx VCU1525 FPGA, our design achieves a throughput of 6.7 Gbps per iteration. Implemented in TSMC 28nm CMOS process at the post-layout stage, a 33.2 Gbps, in one iteration, throughput can be achieved at a clock rate 556 MHz with the core area 1.97 mm2.

Lexical analysis, which converts input text into a list of tokens, plays an important role in many applications, including compilation and data extraction from texts. To recognize token patterns, a lexer incorporates a sequential computation model – automaton as its basic building component. As such, it is considered difficult to parallelize due to the inherent data dependency. Much work has been done to accelerate lexical analysis through parallel techniques. Unfortunately, existing attempts mainly rely on language-specific remedies for input segmentation, which makes it not only tricky for language extension, but also challenging for automatic lexer generation. This paper presents Plex – an automated tool for generating parallel lexers from user-defined grammars. To overcome the inherent sequentiality, Plex applies a fast prescanning phase to collect context information prior to scanning. To reduce the overheads brought by prescanning, Plex adopts a special automaton, which is derived from that of the scanner, to avoid backtracking behavior and exploits data-parallel techniques. The evaluation under several languages shows that the prescanning overhead is small, and consequently Plex is scalable and achieves 9.8-11.5X speedups using 18 threads.

Video captioning is the core technology to drive the development of many important multidisciplinary applications, such as AI-assisted medical diagnosis, storytelling through videos, video question answering, lip-reading, just to name a few. Video captioning employs a hybrid CNN+RNN neural network model to translate video scenes into natural language descriptions. For deep learning inference, a typical approach is running both the CNN and the RNN on a GPU. Such a GPU-only approach often suffers long inference time due to underutilization of the computing power offered by the CPU+GPU heterogeneous system architecture, which is a common architecture in modern computers.This work is an early effort to tackle the performance issue of performing deep learning inference using a hybrid CNN+RNN model on a heterogeneous system with a CPU and a GPU. This is a challenging task because of (1) CNN and RNN exhibit very different computing behaviors. This raises the question of how to split the two models into computing tasks and properly assign the tasks to the CPU and the GPU to minimize the inference time for a video frame, and (2) Data dependency exists between the CNN and the RNN within a video frame, as well as between the adjacent RNNs across two video frames. These data dependencies prohibit full parallelization of the hybrid model. To solve these two problems, we propose two optimizations: a fine-grained scheduling scheme for mapping computation and devices within a video frame, and a pipeline scheduling scheme to exploit maximum parallelism between the execution of the video frames. To facilitate our optimizations, we also develop an accurate regression-based cost model to predict the computation time of CNN/RNN operations and the communication time for moving data between CPU and GPU. Experimental results show that our optimization improves the performance of video captioning by up to 3.24× on the CPU+GPU system, compared with the GPU-only execution.

Hybrid memory systems composed of DRAM and Non-Volatile Memory (NVM) can offer very large memory capacity for data-intensive applications such as graph processing. The performance of parallel graph processing is often affected by straggler tasks due to asymmetrical graph partitioning and sub-graph processing. In hybrid memory systems, the significant difference of performance between DRAM and NVM may exacerbate the load imbalance of parallel graph processing. Traditional load balancing schemes that only aim to balance computing loads among multiple processors are no longer effective in hybrid memory systems.In this paper, we first explore how hybrid memory systems affect the efficiency of existing graph processing systems. We make two observations: 1) Traditional work-stealing schemes may be not efficient enough in hybrid memory systems. Data migration combining with work-stealing can further improve the efficiency of parallel graph processing; 2) Interleaving accesses to different graph partitions due to data dependency have a significant impact on the effectiveness of data migration. To address these problems, we propose NVMGraph, a parallel graph processing scheme to mitigate memory access imbalance among partitions in hybrid memory systems. We first recognize data dependency among all partitions according to graph algorithms and then coalesce the randomly-accessed data required by a working thread in a single partition to mitigate data dependency. To reduce migration cost while still speeding up the straggler task, we only migrate randomly-accessed data blocks in the most frequently-accessed partition from NVM to DRAM. We implement NVMGraph based on Ligra and evaluate it in a hybrid memory system using real NVM devices. Experimental results demonstrate that NVMGraph can improve the performance of graph processing by up to 40.3% compared with the state-of-the-art Ligra and Polymer.

The extended Greatest Common Divisor (GCD) is an extension of the GCD operation, which computes not only the GCD of integers a and b but also the Bezout's coefficients that are integers x and y such that ax + by =3D GCD(a,b). Recently, the large-number extended GCD algorithm is used in the core function of the next-generation blockchain systems and served as the most time-consuming operation. Considering the efficiency, speeding up this operation is urgently desired. However, the extended GCD, which is rarely explored in literature, is extremely hard to parallelize because of long serial operations with strong data dependency. In this paper, we propose a low- latency architecture for the extended GCD of large numbers by utilizing many algorithmic transformations and architectural optimizations. Firstly, a parallel extended GCD algorithm is well studied and modified to be practical in hardware. Secondly, a high-parallel architecture is designed for the selected extended GCD, where the trade-off is well evaluated between computation latency and power consumption. Finally, the architecture is coded using Verilog language and synthesized under the TSMC 28- nm CMOS technology. The experimental results for the 1024-bit extended GCD show that our design significantly outperforms the prior arts.

For several decades, graph and dataflow programming models have been niche topics limited to a small number of highly specialized domains. In recent years, however, the machine learning (ML) revolution and the proliferation of ML libraries has made graph programming accessible to even novice programmers. Before, a beginner programmer may have talked about writing a number-guessing game; today the programmer will describe training an off-the-shelf neural network—a type of graph—for handwriting recognition. There is growing demand from industry and individual users to run programs that are based on ML graphs. This demand is being met by hardware vendors, who are designing larger and increasingly heterogeneous accelerator devices that can efficiently execute graphs. Since its creation, OpenCL has been a key API for bridging the gap between user applications and accelerator hardware. The question, then, is whether OpenCL is an appropriate API for this new breed of graph software running on these large, heterogeneous accelerators. Does OpenCL have the expressive power required to describe an execution graph to accelerator hardware, or does OpenCL serialize graphs and execute them sequentially? This technical presentation argues that it is the former: OpenCL is sufficiently expressive to allow an ML library to describe an execution graph, and OpenCL is sufficiently powerful to execute that graph on a graph accelerator. The OpenCL API is designed around the concept of the user enqueuing commands onto the front of a command-queue. Commands include executing kernels (i.e., functions), and reading, writing, and copying data buffers. The OpenCL device driver removes commands from the back of a command-queue, sets up data transfers to and from the accelerator device, and schedules kernels to execute on the device. The command-queue abstraction can encode execution graphs in one of two ways, depending on whether the command-queue is an in-order command-queue or an out-of-order command-queue. An in-order command-queue guarantees that the effects of the enqueued commands will be as if the commands were executed in the order in which they were enqueued. However, the OpenCL device driver is allowed to reorder commands, provided that reordering does not affect the output. For example, if two kernels do not have a data dependency between them, then they can be executed in reverse order or even in parallel, if the driver and hardware support it. An out-of-order command-queue does not guarantee that commands will appear to have been executed in the order in which they were enqueued. Instead, it is the OpenCL API user’s responsibility to attach events and event wait lists to commands. When a command finishes executing, it triggers its attached event, and when all the events in a command’s event wait list have triggered, then that command is allowed to execute. Both types of command-queues are capable of describing execution graphs. For in-order command-queues, the graph is implied by kernels’ data dependencies; for out-of-order command-queues, the graph is explicitly defined with events. By instrumenting Codeplay’s ComputeAorta[2] OpenCL implementation, it is possible to record OpenCL API calls and to reconstruct the execution graph as seen by the OpenCL device driver. This presentation investigates the execution graphs generated by a simplified handwriting recognition neural network implemented in TensorFlow[1] and running on top of OpenCL via SYCL. Training a neural network and using a neural network for inference produce substantially different execution graphs. Both graphs are considered. The graphs show that data dependencies, opportunities for executing kernels in parallel, and opportunities for reordering kernels are all visible to the driver. It is therefore possible for an OpenCL device driver to schedule work to a hardware accelerator that has been designed for graph execution. It is important to note that OpenCL makes it possible to expose an execution graph to a device driver, but OpenCL cannot guarantee that OpenCL API calls will form a meaningful graph. For example, if a user places many independent data arrays into one memory buffer and enqueues kernels that all operate on the single memory buffer, then information about the execution graph is hidden from OpenCL. Opportunities for parallel execution and kernel reordering are lost. Often, application developers do not write OpenCL code directly, but use libraries that have OpenCL backends. Consequently, it is the responsibility of library developers to ensure that the graph that an application intends to execute is represented correctly on the OpenCL level.

In recent years, Deep Neural Networks (DNNs) have emerged as a widely adopted approach in many application domains. Training DNN models is also becoming a significant fraction of the datacenter workload. Recent evidence has demonstrated that modern DNNs are becoming more complex and the size of DNN parameters (i.e., weights) is also increasing. In addition, a large amount of input data is required to train the DNN models to reach target accuracy. As a result, the training performance becomes one of the major challenges that limit DNN adoption in real-world applications. Recent works have explored different parallelism strategies (i.e., data parallelism and model parallelism) and used multi-GPUs in datacenters to accelerate the training process. However, naively adopting data parallelism and model parallelism across multiple GPUs can lead to sub-optimal executions. The major reasons are i) the large amount of data movement that prevents the system from feeding the GPUs with the required data in a timely manner (for data parallelism); and ii) low GPU utilization caused by data dependency between layers that placed on different devices (for model parallelism). In this paper, we identify the main challenges in adopting data parallelism and model parallelism on multi-GPU platforms. Then, we conduct a survey including recent research works targeting these challenges. We also provide an overview of our work-in-progress project on optimizing DNN training on GPUs. Our results demonstrate that simple-yet-effective system optimizations can further improve the training scalability compared to prior works.