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Recent advances in miniaturization of IR imaging technology have led to a growing market for mini thermal-imaging sensors. In that respect, Sofradir development on smaller pixel pitch has made much more compact products available to the users. When this competitive advantage is mixed with smaller coolers, made possible by HOT technology, we achieved valuable reductions in the size, weight and power of the overall package. At the same time, we are moving towards a global offer based on digital interfaces that provides our customers simplifications at the IR system design process while freeing up more space. This paper discusses recent developments on hot and small pixel pitch technologies as well as efforts made on compact packaging solution developed by SOFRADIR in collaboration with CEA-LETI.

An innovative process development for sub-2μm CMOS imager sensors is described, leading to tremendous improvements on main pixel parameters like conversion gain, saturation charge, sensitivity, dark current and noise. A full 3MP demonstrator with 1.75μm pixel pitch and 1.45μm pixel pitch have been successfully designed, fabricated and characterized.

The recent development of BiCMOS and advanced bipolar and merged bipolar CMOS and DMOS technologies requires the enhancement of both models and parameter extraction strategies for the bipolar device. In order to take into account special behavior such as the base push-out effect or the nonideal base current, new features have been added to the classical SPICE BJT (bipolar junction transistor) model. A flexible software tool has been developed to allow the use of different parameter extraction schemes suitable for a wide range of device behaviors. Experimental validations have been performed in DC analysis. The RMS (root mean square) error on current gain is less than 2%. >

In deep submicron CMOS and BiCMOS technologies, antenna effects affect the floating gate charge of conventional floating gate test structures, dedicated to capacitor matching measurement. In this paper, a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, the testing method and results are given for several capacitor layouts (poly-poly and metal-metal).