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Energy-efficiency has become a major challenge in modern computer systems. To address this challenge, candidate systems increasingly integrate heterogeneous cores in order to satisfy diverse computation requirements by selecting cores with suitable features. In particular, single-ISA heterogeneous multicore processors such as ARM big.LITTLE have become very attractive since they offer good opportunities in terms of performance and power consumption trade-off. While existing works already showed that this feature can improve system energy-efficiency, further gains are possible by generalizing the principle to higher levels of heterogeneity. The present paper aims to explore these gains by considering single-ISA heterogeneous multicore architectures including three different types of cores. For this purpose, we use the Samsung Exynos Octa 5422 chip as baseline architecture. Then, we model and evaluate Cortex A7, A9, and A15 cores using the gem5 simulation framework coupled to McPAT for power estimation. We demonstrate that varying the level of heterogeneity as well as the different core ratio can lead to up to 2.3x gains in energy efficiency and up to 1.5x in performance. This study further provides insights on the impact of workload nature on performance/energy trade-off and draws recommendations concerning suitable architecture configurations. This contributes in fine to guide future research towards dynamically reconfigurable HSAs in which some cores/clusters can be disabled momentarily so as to optimize certain metrics such as energy efficiency. This is of particular interest when dealing with quality-tunable algorithms in which accuracy can be then traded for compute effort, thereby enabling to use only those cores that provide the best energy-efficiency for the chosen algorithm., Comment: 11 pages, 6 figure, 2 tables

A simulator used to simulate cloud applications described using the Amalthea application model on top of a cloud computing architecture. It is built on top of the SimGrid simulator.

Resource allocation is today an integral part of cloud infrastructures management to efficiently exploit resources. Cloud infrastructures centers generally use custom built heuristics to define the resource allocations. It is an immediate requirement for the management tools of these centers to have a fast yet reasonably accurate simulation and evaluation platform to define the resource allocation for cloud applications. This work proposes a framework allowing users to easily specify mappings for cloud applications described in the AMALTHEA format used in the context of the DreamCloud European project and to assess the quality for these mappings. The two quality metrics provided by the framework are execution time and energy consumption., Comment: 2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing DREAMCloud 2016 (arXiv:cs/1601.04675)

A heterogeneous architecture combines, within the same hardware, different kinds of processors, with the goal of delivering fast execution at lower energy budgets. Because energy is such an important parameter of the efficiency of these architectures, much effort has been put into the implementation of techniques to measure the power dissipated by programs that they run. Yet, a vast majority of publications reporting experimental results produced on heterogeneous architectures either resort to simulations or rely on hardware counters; physical measurements are rare. In this paper, we introduce an apparatus - hardware and software - that we have been using to measure energy consumption in Odroid-based big.LITTLE architectures running the Android execution environment. This infra-structure is affordable and reliable. To demonstrate its viability, we show how we can use it to build oracles, i.e., a map that assigns different parts of a program to the hardware configuration that minimizes its energy consumption.

The spectrum of scientific disciplines where computer-based simulation and prediction play a central role is broad: biology, medicine, high energy physics, climatology, astronomy, etc. In the near future, expected exascale supercom-puters will make it possible to address scientific problems that are more complex than ever. However, a major challenge on the path to such supercomputers is the required high energy-efficiency, i.e., maximizing the amount of computational work per watt. To answer this challenge, the position of this paper relies on compute nodes built from inherently low-power technologies. It considers 64-bit ARM processors combined with emerging non-volatile memory (NVM) technologies for main memory, known to be a bottleneck regarding performance and energy. DRAM technology is until now the mainstream option for main memory. However, it will hardly scale beyond a certain level because increased DRAM capacity requires higher refresh rates, which is harmful to power consumption. In such a context, emerging NVMs have become promising alternatives to DRAM thanks to their memory cell density and negligible leakage. This paper evaluates the impact of various main memory technologies, namely DDR4 SDRAM, Phase-Change Memory (PCM), Resistive RAM (RRAM), on computing system performance and memory-related energy consumption. The obtained results show that RRAM is a very promising candidate to mitigate main memory energy consumption, while PCM tends to represent a better candidate for storage level. Compared to DDR4 SDRAM, we observe RRAM can provide comparable system-level performance, while the main memory energy consumption can be reduced by up to 50%.

International audience; In the Algerian republic, scientific and intensive computing are a priority in the strategy of the scientific research between 2013 and 2017. To put into practice this strategy, 32 nodes of high-performance computing were installed in Algeria in particular in the University of Oran. The work that we present in this chapter is our contribution to this priority in the area of intensive embedded computing: static and dynamic mapping heuristics for single chip systems. Thus we present a synthesis of the work done over a few years in a collaboration between the University of Oran, Algeria (LIO and then LAPECI laboratories) and the DART team of LIFL (University Lille 1, CNRS, Inria), and in partnership with the Algerian Center of spatial techniques. We study how to efficiently map intensive applications on network-on-chip based multiprocessor systems-on-chip.