1. A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18$��$m Digital CMOS
- Author
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Andersen, Terje N., Briskemyr, Atle, Telsto, Frode, Bjornsen, Johnny, Bonnerud, Thomas E., Hernes, Bjornar, and Moldsvor, Oystein
- Subjects
FOS: Computer and information sciences ,Hardware Architecture (cs.AR) ,Hardware_INTEGRATEDCIRCUITS ,Hardware_PERFORMANCEANDRELIABILITY ,Hardware_ARITHMETICANDLOGICSTRUCTURES - Abstract
A 12 bit Pipeline ADC fabricated in a 0.18 $��$m pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with 2V_{P-P} signal swing is applied. The occupied silicon area is 0.86mm^2 and the power consumption equals 97mW. A switched capacitor bias current circuit scale the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140MS/s., Submitted on behalf of EDAA (http://www.edaa.com/)
- Published
- 2007
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