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We describe a fabrication stackup for digital logic with 16 superconducting NbTiN layers, self-shunted a-silicon barrier Josephson Junctions (JJs), and low loss, high-$\kappa$ tunable HZO capacitors. The stack enables 400 MJJ/cm$^2$ device density, efficient routing, and AC power distribution on a resonant network. The materials scale beyond 28nm lithography and are compatible with standard high-temperature CMOS processes. We report initial results for two-metal layer NbTiN wires with 50nm critical dimension. A semi-ascendance wire-and-via process module using 193i lithography and 50nm critical dimension has shown cross-section uniformity of 1%=1s across the 300mm wafer, critical temperature of 12.5K, and critical current of 0.1mA at 4.2K. We also present a new design of the resonant AC power network enabled by NbTiN wires and HZO MIM capacitors. The design matches the device density and provides a 30 GHz clock with estimated efficiency of up to 90%. Finally, magnetic imaging of patterned NbTiN ground planes shows low intrinsic defectivity and consistent trapping of vorteces in 0.5 mm holes spaced on a 20 $\mu$m x 20 $\mu$m grid., Comment: 7 pages, 3 figures

We report the design and test of Reciprocal Quantum Logic shift-register yield vehicles consisting of up to 72,800 Josephson junction devices per die, the largest digital superconducting circuits ever reported. Multiple physical layout styles were matched to the MIT Lincoln Laboratory foundry, which supports processes with both four and eight metal layers and minimum feature size of 0.5 {\mu}m. The largest individual circuits with 40,400 junctions indicate large operating margins of $\pm$20% on AC clock amplitude. In one case the data were reproducible to the accuracy of the measurement, $\pm$1% across five thermal cycles using only the rudimentary precautions of passive mu-metal magnetic shielding and a controlled cool-down rate of 3 mK/s in the test fixture. We conclude that with proper mitigation techniques, flux-trapping is no longer a limiting consideration for very-large-scale-integration of superconductor digital logic.