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Recent advances in algorithm-hardware co-design for deep neural networks (DNNs) have demonstrated their potential in automatically designing neural architectures and hardware designs. Nevertheless, it is still a challenging optimization problem due to the expensive training cost and the time-consuming hardware implementation, which makes the exploration on the vast design space of neural architecture and hardware design intractable. In this paper, we demonstrate that our proposed approach is capable of locating designs on the Pareto frontier. This capability is enabled by a novel three-phase co-design framework, with the following new features: (a) decoupling DNN training from the design space exploration of hardware architecture and neural architecture, (b) providing a hardware-friendly neural architecture space by considering hardware characteristics in constructing the search cells, (c) adopting Gaussian process to predict accuracy, latency and power consumption to avoid time-consuming synthesis and place-and-route processes. In comparison with the manually-designed ResNet101, InceptionV2 and MobileNetV2, we can achieve up to 5% higher accuracy with up to 3x speed up on the ImageNet dataset. Compared with other state-of-the-art co-design frameworks, our found network and hardware configuration can achieve 2% ~ 6% higher accuracy, 2x ~ 26x smaller latency and 8.5x higher energy efficiency.

\ce{MoS_2} is a two dimensional material with a band gap depending on the number of layers and tunable by an external electric field. The experimentally observed intralayer band-to-band tunneling and interlayer band-to-band tunneling in this material present an opportunity for new electronic applications in tunnel field effect transistors. However, such a widely accepted concept has never been supported up by theoretical investigations based on first principles. In this work, using density functional theory, in conjunction with non-equilibrilibrium Green's function techniques and our electric field gating method, enabled by a large-scale computational approach, we study the relation between band alignment and transmission in planar and side-stack \ce{MoS_2} $p$-$i$-$n$ junction configurations. We demonstrate the presence of negative differential resistance for both in-plane and interlayer current, a staple characteristic of tunnel diode junctions, and analyze the physical origin of such an effect. Electrostatic potentials, the van der Waals barrier, and complex band analysis are also examined for a thorough understanding of Esaki Diodes., Comment: 8 pages, 8 figures

Due to the complexity and highly demand in quality of the bogie assembly of railway vehicles, CRRC Nanjing Puzhen Co., Ltd has developed an intelligent assembly system for railway vehicle bogies. The system can accomplish the intelligent transportation of the bogie parts by the robot on the shelf and the software system developed by ourselves. At the same time, it can also carry out wireless information interaction with the control center and generate process files automatically according to process tasks transmitted by the control center. Besides, a series of key technologies including 3D process documents intelligent push technology, intelligent material box online detection technology, human-machine collaboration technology and system integration control technology have been conquered, which realized the high efficient production and reduced costs of railway vehicle bogie assembly.

Industrial robots are increasingly being used in automated production line with their high flexibility and low cost However the poor features of repeat positioning accuracy and absolute positioning accuracy of industrial robots have been a bottleneck restricting its application in higher accuracy situation Many scholarshave studied methods to improve the accuracy of robot But there is congenital defect for industrial robots when their accuracy is further improved by compensation and few people pay attention to this In this article the backlash of industrial robot joint is discussed and its impact on accuracy compensation is analyzed Finally the method of eliminating the backlash and further improving the robot s accuracy based on joint feedback is proposed

Monte Carlo (MC) methods such as Markov chain Monte Carlo (MCMC) and sequential Monte Carlo (SMC) have emerged as popular tools to sample from high dimensional probability distributions. Because these algorithms can draw samples effectively from arbitrary distributions in Bayesian inference problems, they have been widely used in a range of statistical applications. However, they are often too time consuming due to the prohibitive costly likelihood evaluations, thus they cannot be practically applied to complex models with large-scale datasets. Currently, the lack of sufficiently fast MCMC methods limits their applicability in many modern applications such as genetics and machine learning, and this situation is bound to get worse given the increasing adoption of big data in many fields. The objective of this dissertation is to develop, design and build efficient hardware architectures for MCMC-based algorithms on Field Programmable Gate Arrays (FPGAs), and thereby bring them closer to practical applications. The contributions of this work include: 1) Novel parallel FPGA architectures of the state-of-the-art resampling algorithms for SMC methods. The proposed architectures allow for parallel implementations and thus improve the processing speed. 2) A novel mixed precision MCMC algorithm, along with a tailored FPGA architecture. The proposed design allows for more parallelism and achieves low latency for a given set of hardware resources, while still guaranteeing unbiased estimates. 3) A new variant of subsampling MCMC method based on unequal probability sampling, along with a highly optimized FPGA architecture. The proposed method significantly reduces off-chip memory access and achieves high accuracy in estimates for a given time budget. This work has resulted in the development of hardware accelerators of MCMC and SMC for very large-scale Bayesian tasks by applying the above techniques. Notable speed improvements compared to the respective state-of-the-art CPU and GPU implementations have been achieved in this work. Open Access